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Part: HYB514171BJ-50

Category:
 Analog & Mixed-Signal Processing
   -> Amplifiers
     -> High Dynamic Range Amplifiers

Description: 256k X 16-bit Dynamic RAM

Company: Siemens (acquired by Infineon Technologies Corporation)

Datasheet: Download HYB514171BJ-50 datasheet     File size : 391 kB

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Datasheet text preview:
256k × 16-Bit Dynamic RAM
HYB 514171BJ-50/-60
Advanced Information · · · · 262 144 words by 16-bit organization 0 to 70 °C operating temperature Fast access and cycle time RAS access time: 50 ns (-50 version) 60 ns (-60 version) · Standby power dissipation 11 mW standby (TTL) 5.5 mW max. standby (CMOS) · Output unlatched at cycle end allows two-dimensional chip selection · Read, write, read-modify write, CAS-before-RAS refresh, RAS-only refresh, hidden-refresh and fast page mode capability · 2 CAS / 1 WE control · All inputs and outputs TTL-compatible · 512 refresh cycles / 16 ms · Plastic Packages: P-SOJ-40-1 400 mil width
· CAS access time: 15ns (-50, -60 version) · Cycle time: 95 ns (-50 version) 110 ns (-60 version) · Fast page mode cycle time 35 ns (-50 version) 40 ns (-60 version) · Single + 5.0 V (± 10 %) supply with a built-in VBB generator · Low Power dissipation max. 1045 mW active (-50 version) max. 935 mW active (-60 version)
The HYB 514171BJ is a 4 MBit dynamic RAM organized as 262 144 words by 16-bit. The HYB 514171BJ utilizes CMOS silicon gate process as well as advanced circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 514171BJ to be packed in a standard plastic 400 mil wide P-SOJ-40-1 package. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented features include single + 5 V (± 10 %) power supply, direct interfacing with high performance logic device families such as Schottky TTL.
Semiconductor Group
1
1998-10-01
HYB 514171BJ-50/-60 256k × 16 DRAM
Ordering Information Type HYB 514171BJ-50 HYB 514171BJ-60 Truth Table RAS H L L L L L L L L LCAS H H L H L L H L L UCAS H H H L L H L L L WE H H H H H L L L H OE H H L L L H H H H I/O1 - I/O8 High-Z High-Z Dout High-Z Dout Din Don't care Din High-Z I/O9 - I/O16 High-Z High-Z High-Z Dout Dout Don't care Din Din High-Z Operation Standby Refresh Lower byte read Upper byte read Word read Lower byte write Upper byte write Word write - Ordering Code Q67100-Q2021 Q67100-Q727 Package P-SOJ-40-1 400 mil P-SOJ-40-1 400 mil Description 50 ns 256k × 16 DRAM 60 ns 256k × 16 DRAM
Pin Names A0 - A8 RAS UCAS, LCAS WE OE I/O1 - I/O16 Address Inputs Row Address Strobe Column Address Strobe Read/Write Input Output Enable Data Input/Output Power Supply (+ 5 V) Ground (0 V) No Connection
VCC VSS
N.C.
Semiconductor Group
2
1998-10-01
HYB 514171BJ-50/-60 256k × 16 DRAM
P-SOJ-40-1
V CC I/O1 I/O2 I/O3 I/O4 V CC I/O5 I/O6 I/O7 I/O8 N.C. N.C. WE RAS N.C. A0 A1 A2 A3 V CC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 V SS 39 I/O16 38 I/O15 37 I/O14 36 I/O13 35 V SS 34 I/O12 33 I/O11 32 I/O10 31 I/O9 30 N.C. 29 LCAS 28 UCAS 27 OE 26 A8 25 A7 24 A6 23 A5 22 A4 21 V SS
SPP02811
Pin Configuration (top view)
Semiconductor Group
3
1998-10-01


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