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Part: HYB3117805BJ-50
Category:
Analog & Mixed-Signal Processing
-> Amplifiers
-> High Dynamic Range Amplifiers
Description: 2m X 8 - Bit Dynamic RAM 2k Refresh
Company: Siemens (acquired by Infineon Technologies Corporation)
Datasheet: Download HYB3117805BJ-50 datasheet File size : 1211 kB
Request For quote: Find where to buy HYB3117805BJ-50
Datasheet text preview:
2M x 8 - Bit Dynamic RAM 2k Refresh (Hyper Page Mode- EDO)
Advanced Information
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HYB3117805BSJ -50/-60/-70
2 097 152 words by 8-bit organization 0 to 70 °C operating temperature Performance: -50 tRAC tCAC tAA tRC tHPC RAS access time CAS access time Access time from address Read/Write cycle time Hyper page mode (EDO) cycle time 50 13 25 84 20 -60 60 15 30 104 25 -70 70 20 35 124 30 ns ns ns ns ns
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Single + 3.3 V (± 0.3 V) supply Low power dissipation max. 432 mW active (-50 version) max. 396 mW active (-60 version) max. 360 mW active (-70 version) 7.2 mW standby (LV-TTL) 3.6 mW standby (CMOS) Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh, self refresh and test mode Hyper page mode (EDO) capability All inputs, outputs and clocks fully TTL-compatible 2048 refresh cycles / 32 ms (2k-Refresh) Plastic Package: P-SOJ-28-3 400 mil
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Semiconductor Group
1
1.96
HYB3117805BSJ-50/-60/-70 2M x 8-EDO DRAM
The HYB 3117805BSJ is a 16 MBit dynamic RAM organized as 2 097 152 words by 8-bits. The HYB 3117805BSJ utilizes a submicron CMOS silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 3117805BSJ to be packaged in a standard SOJ 28 plastic package with 400 mil width. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. System-oriented features include single + 3.3 V (± 0.3 V) power supply, direct interfacing with high-performance logic device families such as Schottky TTL. Ordering Information Type HYB 3117805BJ-50 HYB 3117805BJ-60 HYB 3117805BJ-70 Pin Names A0-A10 A0-A9 RAS OE I/O1-I/O8 CAS WE Row Address Inputs Column Address Inputs Row Address Strobe Output Enable Data Input/Output Column Address Strobe Read/Write Input Power Supply (+ 3.3 V) Ground (0 V) not connected Ordering Code Q67100-Q1151 Q67100-Q1152 Package P-SOJ-28-3 400 mil P-SOJ-28-3 400 mil P-SOJ-28-3 400 mil Descriptions DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns)
VCC VSS
N .C.
Semiconductor Group
2
HYB3117805BSJ-50/-60/-70 2M x 8-EDO DRAM
P-SOJ-28-3
400 mil
VCC I/O1 I/O2 I/O3 I/O4 WE RAS N.C. A10 A0 A1 A2 A3 VCC
O 1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VSS I/O8 I/O7 I/O6 I/O5 CAS OE A9 A8 A7 A6 A5 A4 VSS
Pin Configuration
Semiconductor Group
3
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