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Part: M21L216128A-15J
Category:
Memory
-> SRAM
Description: Org. = 128KbX16 ;; Description = SRAM 3V ;; Speed = 10ns ;; Package = 44-TSOPII
Company: EliteMT
Datasheet: Download M21L216128A-15J datasheet File size : 54 kB
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Datasheet text preview:
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SRAM
FEATURES
M21L216128A 128 K x 16 SRAM
HIGH SPEED CMOS SRAM
ORDERING INFORMATION
44-pin 400mil SOJ 44-pin 400mil TSOP (TypeII) Acess Time (ns) 10
T T T T T T T T T T
Fast access times : 10, 12, and 15ns Fast OE access times : 5, 6, and 7ns Single +3.3V ± 0.3V power supply Fully static -- no clock or timing strobes necessary All inputs and outputs are TTL-compatible Three state outputs Center power and ground pins for greater noise immunity Easy memory expansive with CE and OE options Automatic CE power down
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PRODUCT NO. M21L216128A-10J M21L216128A-10T M21L216128A-12J M21L216128A-12T M21L216128A-15J M21L216128A-15T
PACKING TYPE SOJ TSOP
12
SOJ TSOP SOJ TSOP
15
GENERAL DESCRIPTION
The M21L216128A is a high speed, low power asynchronous SRAM containing 2,097,152 bits and organized as 131,072 by 16 bits, it is produced by high performance CMOS process. This device offers center power and ground pins for improved performance and noise immunity. Static design eliminates the need for external clocks or timing strobes. For increased system flexibility and eliminating bus contention problem s, this device offers chip enable ( CE ), separate byte enable controls ( LB and HE ) and output enable ( OE ) with this organization.
PIN ASSIGNMENT
SOJ Top View
A4 A3 A2 A1 A0 CE DQ1 DQ2 DQ3 DQ4 VCC GND DQ5 DQ6 DQ7 DQ8 WE A1 6 A1 5 A1 4 A1 3 A1 2
TSOP (TypeII) Top View
A5 A6 A7 OE HB LB DQ 1 6 DQ 1 5 DQ 1 4 DQ 1 3 GND VC C DQ 1 2 DQ 1 1 DQ 1 0 DQ9 NC A8 A9 A1 0 A1 1 NC A4 A3 A2 A1 A0 CE D Q1 D Q2 D Q3 D Q4 VC C GND DQ5 DQ6 DQ7 DQ8 WE A1 6 A1 5 A1 4 A1 3 A1 2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A5 A6 A7 OE HB LB DQ16 DQ15 DQ14 DQ13 GND VCC DQ12 DQ11 DQ10 D Q9 NC A8 A9 A1 0 A1 1 NC
Elite Semiconduture Memory Technology Inc
Publication Date : Sep. 2000 Revision : 1.0 1/14
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Block Diagram
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M21L216128A
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M E M O R Y ARRAY
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Pin Descriptions
Pin No. 1 - 5, 18 - 22, 24-27, 42 - 44 6 7 - 10, 13 - 16, 29 - 32, 35 - 38 17 39 40 Sym bol A0 - A16
CE
Description Address Inputs Chip Enable Input
DQ1 - DQ16
WE LB HB
Data Inputs/Outputs Write Enable Input Lower Byte Enable Input (DQ1 to DQ8) Higher Byte Enable Input (DQ9 to DQ16) Output Enable Input Power Ground No Connection
41 11, 33 12, 34 23, 28
OE
VCC GND NC
Elite Semiconduture Memory Technology Inc
Publication Date : Sep. 2000 Revision : 1.0 2/14
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ABSOLUTE MAXIMUM RATINGS *
Voltage on VCC Supply Relative to Vss ... ......-0.5V to +4.6V VIN ......-0.5V to VCC+1.0V Operating Temperature, Topr ..... 0 °C to +70 °C Storage Temperature (plastic) ..........-55 °C to +125 °C Junction Temperature .........+125 °C Power Dissipation .........1.0W Short Circuit Output Current ...50mA
M21L216128A
*Stresses greater than those listed under Absolute Maxim um. Ratings may permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATIONS
(All Temperature Ranges ; VCC = 3.3V ± 0.3V unless otherwise noted) DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage 0V VIN VCC Output(s) disable 0V VOUT VCC IOH = -4.0 mA IOL = 8.0 mA CONDITIONS SYM BOL VIH VII I LI I LO VOH VOL VCC 3.0 MIN 2.2 -0.5 -10 -5 2.4 0.4 3.6 MAX VCC+0.5 0.8 10 5 UNITS NOTES V V µA µA V V V 1 1 1 1,2 1,2
DESCRIPTION Power Supply Current : Operating TTL Standby CMOS Standby
CONDITIONS Device selected; CE VIL; VCC=MAX; f=fMAX ; outputs open
CE VIH; VCC=MAX; f=fMAX CE1 VCC-0.2; VCC = MAX; all other inputs GND +0.2 or VCC -0.2; all inputs static ; f=0
SYM BOL -10 ICC I SB1 I SB2 190 35 10
MAX -12 160 30 10 -15 130 25 10
UNITS mA mA mA
NOTES 3
CAPACITANCE
DESCRIPTION Input Capacitance Input/Output Capacitance(DQ) CONDITIONS TA= 25°C ; f=1 MHz VCC=3.3V SYM BOL CI CI/O MAX 6 8 UNITS NOTES pF pF 4 4
Elite Semiconduture Memory Technology Inc
Publication Date : Sep. 2000 Revision : 1.0 3/14
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