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Part: M13S128168A-5T
Category:
Memory
-> DRAM
-> DDR SDRAM
-> 128 Mb
Description: Org. = 8MbX16 ;; Description = DDR 2.5V ;; Refresh = ;; Speed/ Clock Freq. = 166/133 MHZ ;; Package = 66-TSOPII
Company: EliteMT
Datasheet: Download M13S128168A-5T datasheet File size : 24 kB
Request For quote: Find where to buy M13S128168A-5T
Datasheet text preview:
ESMT
Revision History
Revision 0.1 (15 Jan. 2002) - Original
Preliminary
M13S128168A
Revision 0.2 (19 Nov. 2002) -changed ordering information & DC/AC characteristics Revision 0.1 M13S128168A - 5T M13S128168A - 6T Revision 0.2 M13S128168A - 6T M13S128168A - 7.5AB
Revision 0.3 (8 Aug. 2003) -Change IDD6 from 3mA to 5mA.
Revision 0.4 (27 Aug. 2003) -Change ordering information & DC / AC characteristics.
Revision 1.0 (21 Oct. 2003) -Modify tWTR from 2tck to 1tck.
Revision 1.1 (10 Nov. 2003) -Correct some refresh interval that is not revised. -Correct some CAS Lantency that is not revised.
Elite Semiconductor Memory Technology Inc.
Publication Date : Nov. 2003 Revision : 1.1 1/48
ESMT
DDR SDRAM
Features
JEDEC Standard
Preliminary
M13S128168A 2M x 16 Bit x 4 Banks Double Data Rate SDRAM
Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) On-chip DLL Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition Quad bank operation CAS Latency : 3 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8 All inputs except data & DM are sampled at the rising edge of the system clock(CLK) Data I/O transitions on both edges of data strobe (DQS) DQS is edge-aligned with data for reads; center-aligned with data for WRITE Data mask (DM) for write masking only VDD = 2.375V ~ 2.75V, VDDQ = 2.375V ~ 2.75V Auto & Self refresh 7.8us refresh interval SSTL-2 I/O interface 66pin TSOPII package
Operating Frequencies :
PRODUCT NO. M13S128168A -5T M13S128168A -6T MAX FREQ 200MHz 166MHz VDD 2.5V PACKAGE TSOPII
Elite Semiconductor Memory Technology Inc.
Publication Date : Nov. 2003 Revision : 1.1 2/48
ESMT
Functional Block Diagram
CLK CLK CKE Address
Mode Register & Extended Mode Register
Preliminary
M13S128168A
Clock Generator
Bank D Bank C Bank B Row Decoder Row Address Buffer & Refresh Counter
Bank A
Sense Amplifier Command Decoder Control Logic
CS RAS CAS WE
Data Control Circuit
Input & Output Buffer
Latch Circuit
Column A ddress Buffer & Refresh Counter
DM
Column Decoder
DQ
CLK, CLK
DLL
DQS
DQS
Pin Arrangement
x16
VDD DQ 0 VDDQ DQ 1 DQ 2 VSSQ DQ 3 DQ 4 VDDQ DQ 5 DQ 6 VSSQ DQ 7 NC VDDQ LD QS NC VDD NC LD M WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
x16
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ 9 VDDQ DQ 8 NC VSSQ UDQ S NC VREF VSS UD M CL K CL K CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS
66 PIN TSOP(II) (400mil x 875mil) (0.65 mm PIN PITCH)
Elite Semiconductor Memory Technology Inc.
Publication Date : Nov. 2003 Revision : 1.1 3/48
Others parts begin by m1
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