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Part: PDSP16340

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Company: Zarlink Semiconductor

Datasheet: Download PDSP16340 datasheet     File size : 390 kB

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Datasheet text preview:
THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS
FEBPDSP16340 RUARY 1995
ADVANCE INFORMATION
DS3710 - 2.1
PDSP16340
POLAR TO CARTESIAN CONVERTER
(Supersedes version in December 1993 Digital Video & Digital Signal Processing IC Handbook, HB3923-1)
The PDSP16340 can be configured to perform either a coordinate conversion function, or simply to provide a sine / cosine look-up table. When employed as a coordinate conversion processor, the device converts data from 16 bit polar coordinates (R,Ø) into 16 bit cartesian coordinates (Real, Imaginary). The translation is illustrated in Fig. 1, and uses the formula:Xr = R cos(Ø) Xi = R sin(Ø) In look-up table mode, the user enters 16 bit phase data, and the chip outputs the corresponding sine and cosine values. A typical application is shown in Fig. 5. The PDSP16340 is pipelined to process a continuous stream of data at 20 MHz, and outputs a new (16 + 16) bit result every clock cycle. The RANGE control signal allows the user to select the input range most appropriate to the system. Data is produced in Two's Complement Fractional format.
FEATURES
Provides R cos(Ø) and R sin(Ø) in 16 bit streams using a CORDIC processor Look-up table equivalent to 64k by 32 bit ROM 20MHz clock rate Tri-state outputs and independent data enables 84 Pin PGA or 132 pin QFP
ASSOCIATED PRODUCTS
PDSP16330 Pythagoras Processor Programmable FIR Filter FFT Processor I/Q Splitter and NCO 16 Bit Complex Multiplier Complex Accumulator
APPLICATIONS
Digital Signal Processing Radar Systems Sonar Systems Robotics Medical Imaging
PDSP16256 PDSP16510 PDSP16350 PDSP16116 PDSP16318
Imaginary
Phase Magnitude
CORDIC PROCESSOR ARRAY
Magnitude Adjust
Xi R
Ø Xr
Fig. 1. Cartesian to Polar Coordinates
Real
Real (Cosine)
Imaginary (Sine)
Fig. 2. Simplified Block Diagram
1
PDSP16340
N
PEN
MODE
M1
M3
M5
VDD
M8
GND
M10
M12
M14
VOUT
SAT
M
RANGE
M0
M2
M4
M6
M7
M9
M11
M13
M15
VIN
L
P15
O/C
XI15
XI14
K
P13
P14
XI13
XI12
J
P11
P12
XI11
XI10
H
GND
P10
XI9
GND
G
P9
P8
XI8
XI7
F
VDD
P7
XI6
VDD
E
P6
P5
XI4
XI5
D
P4
P3
XI2
XI3
C
P2
P1
XI0
XI1
B
P0
XR15
XR13
XR11
XR9
XR7
XR6
XR4
XR2
XR0
MEN
A
CLOCK
GND
XR14
XR12
XR10
VDD
XR8
GND
XR5
XR3
XR1
OEI
OER
1
2
3
4
5
6
7
8
9
10
11
12
13
Fig. 3A Device Pinout - Bottom View (84 pin PGA - AC84)
2


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