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Part: EDI8F32512C-35
Category:
Memory
-> SRAM
-> Modules
-> SRAM Modules
Description: Organization = 512Kx32 ;; Speed (ns) = 20-35 ;; Volt = 5 ;; Package = 72 Simm ;; Temp = C ;;
Company: White Electronic Designs Corporation
Datasheet: Download EDI8F32512C-35 datasheet File size : 576 kB
Request For quote: Find where to buy EDI8F32512C-35
Datasheet text preview:
EDI8F32512C
512Kx32 SRAM Module
Features
512Kx32 bit CMOS Static Random Access Memory · Access Times: 15, 17, 20, 25 and 35ns · Individual Byte Selects · Fully Static, No Clocks · TTL Compatible I/O High Density Package · 72 Pin ZIP, No. 173 · 72 lead SIMM, No. 174 (Gold Option) · Common Data Inputs and Outputs Single +5V (±10%) Supply Operation
512Kx32 Static RAM CMOS, High Speed Module
The EDI8F32512C is a high speed 16 megabit Static RAM module organized as 512K words by 32 bits. This module is constructed from four 512Kx8 Static RAMs in SOJ packages on an epoxy laminate (FR4) board. Four chip enables (EØ-E3) are used to independently enable the four bytes. Reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects. The EDI8F32512C is offered in 72 pin ZIP and 72 lead SIMM packages, which enable 16 megabits of memory to be placed in less than 1.3 square inches of board space. All inputs and outputs are TTL compatible and operate from a single 5V supply. Fully asynchronous circuitry requires no clocks or refreshing for operation and provides equal access and cycle times for ease of use. Pins PD1- PD4, are used to identify module memory density in applications where alternate modules can be interchanged.
Pin Configurations and Block Diagram
Pin Names
NC PD4 PD1 DQØ DQ1 DQ2 DQ3 VCC A7 A8 A9 DQ4 DQ5 DQ6 DQ7 W A14 EØ E2 A16 VSS DQ16 DQ17 DQ18 DQ19 A10 A11 A12 A13 DQ20 DQ21 DQ22 DQ23 VSS NC NC 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 NC PD3 VSS PD2 DQ8 DQ9 DQ10 DQ11 AØ A1 A2 DQ12 DQ13 DQ14 DQ15 VSS A15 E1 E3 A17 G DQ24 DQ25 DQ26 DQ27 A3 A4 A5 VCC A6 DQ28 DQ29 DQ30 DQ31 A18 NC
AØ-A18 EØ-E3 W G DQØ-DQ31 VCC VSS NC
AØ-A18 W G
19
Address Inputs Chip Enables Write Enable Output Enable Common Data Input/Output Power (+5V±10%) Ground No Connection
DQØ-DQ7
8
EØ DQ8-DQ15
8
E1 DQ16-DQ23
8
E2 DQ24-DQ31
8
PD1, PD2,PD4 = Open PD3 = VSS
E3
Electronic Designs Incorporated · One Research Drive · Westborough, MA 01581 USA · 508-366-5151 · FAX 508-836-4850 · Electronic Designs Europe Ltd. · Shelley House, The Avenue · Lightwater, Surrey GU18 5RF United Kingdom · 01276 472637 · FAX 01276 473748 http://www.electronic-designs.com 1 EDI8F32512C Rev. 7 12/97 ECO #9492
Absolute Maximum Ratings*
Voltage on any pin relative to VSS Operating Temperature TA (Ambient) Commercial Industrial Storage Temperature, Plastic Power Dissipation Output Current -0.5V to 7.0V 0°C to +70°C -40°C to +85°C -55°C to +125°C 5.0 Watts 20 mA
Recommended DC Operating Conditions
Parameter Sym Supply Voltage VCC Supply Voltage VSS Input High Voltage VIH Input Low Voltage VIL Min 4.5 0 2.2 -0.3 Typ 5.0 0 --Max Units 5.5 V 0 V 6.0 V 0.8 V
*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
AC Test Conditions
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load
(note: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF)
VSS to 3.0V 5ns 1.5V 1TTL, CL = 30pF
DC Electrical Characteristics
Parameter Operating Power Supply Current Standby (TTL) Power Supply Current Full Standby Power Supply Current CMOS Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage
*Typical: TA = 25°C, VCC = 5.0V
Sym Conditions ICC1 W, E = VIL, II/O = 0mA, Min Cycle ICC2 E VIH, VIN VIL or VIN VIH ICC3 E VCC-0.2V VIN VCC-0.2V or VIN 0.2V ILI VIN = 0V to VCC ILO V I/O = 0V to VCC VOH IOH = -4.0mA VOL IOL = 8.0mA
Min
Typ*
--2.4 --
(BiCMOS) -----
Max 800 300 80 120 ±20 ±20 -0.4
Units mA mA mA mA µA µA V V
Truth Table
E H L L L W X H L H G X L X H Mode Standby Read Write Output Deselect Output HIGH Z DOUT DIN HIGH Z Power ICC2/ICC3 ICC1 ICC1 ICC1
Capacitance
(f=1.0MHz, VIN=VCC or VSS)
Parameter Address Lines Data Lines Chip Enable Line Write Line Sym CI CD/Q CC CN Max 45 20 20 45 Unit pF pF pF pF
These parameters are sampled, not 100% tested.
EDI8F32512C
512Kx32 SRAM Module
2 EDI8F32512C Rev. 7 12/97 ECO #9492
EDI8F32512C
512Kx32 SRAM Module
AC Characteristics Read Cycle
Parameter Read Cycle Time Address Access Time Chip Enable Access Chip Enable to Output in Low Z (1) Chip Disable to Output in High Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z(1)
Notes: 1. Parameter guaranteed, but not tested.
Symbol JEDEC Alt. TAVAV TRC TAVQV TAA TELQV TACS TELQX TCLZ TEHQZ TCHZ TAVQX TOH TGLQV TOE TGLQX TOLZ TGHQZ TOHZ
15ns Min Max 15 15 15 3 6 3 6 0 6
17ns Min Max 17 17 17 3 7 3 6 0 7
20ns Min Max 20 20 20 3 10 3 8 0 8
25ns Min Max 25 25 25 3 12 3 10 0 10
35ns Min Max Units 35 ns 35 ns 35 ns 3 ns 15 ns 3 ns 12 ns 0 ns 12 ns
Read Cycle 1 - W High, G, E Low
TAVAV A ADDRESS 1 TAVQV Q ADDRESS 2 TAVQX DATA 1 DATA 2
Read Cycle 2 - W High
A E TELQV TELQX G TGLQV TGLQX Q TGHQZ TEHQZ
TAVQV
3 EDI8F32512C Rev. 7 12/97 ECO #9492
AC Characteristics Write Cycle
Symbol JEDEC Alt. TAVAV TWC TELWH TCW TWLEH TCW Address Setup Time TAVWL TAS TAVEL TAS Address Valid to End of Write TAVWH TAW TAVEH TAW Write Pulse Width TWLWH TWP TELEH TWP Write Recovery Time TWHAX TWR TEHAX TWR Data Hold Time TWHDX TDH TEHDX TDH Write to Output in High Z (1) TWLQZ TWHZ Data to Write Time TDVWH TDW TDVEH TDW Output Active from End of Write (1) TWHQX TWLZ Parameter Write Cycle Time Chip Enable to End of Write
Notes: 1. Parameter guaranteed, but not tested.
15ns Min Max 15 8 8 0 0 8 8 10 10 0 0 0 0 06 7 7 3
17ns Min Max 17 12 12 0 0 12 12 12 12 0 0 0 0 08 8 8 3
20ns Min Max 20 15 15 0 0 15 15 15 15 0 0 0 0 08 9 9 3
25ns 35ns Min Max Min Max 25 35 20 25 20 25 0 0 0 0 15 20 15 20 15 20 15 20 0 0 0 0 0 0 0 0 0 12 0 15 10 20 10 20 3 3
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Write Cycle 1 - W Controlled
TAVAV A E TELWH TAVWH W TAVWL D TWLQZ Q HIGH Z TWLWH TDVWH D A T A VALID TWHQX TWHDX TWHAX
EDI8F32512C
512Kx32 SRAM Module
4 EDI8F32512C Rev. 7 12/97 ECO #9492
EDI8F32512C
512Kx32 SRAM Module
Write Cycle 2 - E Controlled
TAVAV A TAVEL E TAVEH TWLEH W TDVEH D Q HIGH Z DATA VALID TEHDX TEHAX TELEH
5 EDI8F32512C Rev. 7 12/97 ECO #9492
Others parts begin by ed
ED-1 ED-2 ED-3 ED-4 ED-5 ED-6
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