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Part: SA555D
Category:
Timing Circuits
-> Timers
Description: ti SA555, Precision Timer
Company: Texas Instruments, Inc.
Datasheet: Download SA555D datasheet File size : 70 kB
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Datasheet text preview:
NE555, SA555, SE555 PRECISION TIMERS
SLFS022D SEPTEMBER 1973 REVISED JUNE 2003
D D D D
Timing From Microseconds to Hours Astable or Monostable Operation Adjustable Duty Cycle TTL-Compatible Output Can Sink or Source Up To 200 mA
NE555 . . . D, P, PS, OR PW PACKAGE SA555 . . . D OR P PACKAGE SE555 . . . D, JG, OR P PACKAGE (TOP VIEW)
description/ordering information
These devices are precision timing circuits capable of producing accurate time delays or oscillation. In the time-delay or monostable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the astable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor.
GND TRIG OUT RESET
1 2 3 4
8 7 6 5
VCC DISCH THRES CONT
SE555 . . . FK PACKAGE (TOP VIEW)
NC GND NC VCC NC NC TRIG NC OUT NC
4 5 6 3 2 1 20 19 18 17 16
The threshold and trigger levels normally are 15 7 two-thirds and one-third, respectively, of VCC. 14 8 9 10 11 12 13 These levels can be altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set and the output goes high. If the trigger input is above the trigger level and the threshold input is above NC No internal connection the threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all other inputs and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset and the output goes low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground. The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of 5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs.
NC RESET NC CONT NC
NC DISCH NC THRES NC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
NE555, SA555, SE555 PRECISION TIMERS
SLFS022D SEPTEMBER 1973 REVISED JUNE 2003
ORDERING INFORMATION
TA VTHRES MAX VCC = 15 V PDIP (P) SOIC (D) (D) 0°C to 70°C to 70°C 11.2 V SOP (PS) TSSOP (PW) (PW) PDIP (P) 40°C to 85°C 11.2 V SOIC (D) (D) PDIP (P) 55°C to 125°C 10.6 V SOIC (D) (D) CDIP (JG) LCCC (FK) PACKAGE Tube of 50 Tube of 75 Reel of 2500 Reel of 2000 Tube of 150 Reel of 2000 Tube of 50 Tube of 75 Reel of 2000 Tube of 50 Tube of 75 Reel of 2500 Tube of 50 Tube of55 ORDERABLE PART NUMBER NE555P NE555D NE555DR NE555PSR NE555PW NE555PWR SA555P SA555D SA555DR SE555P SE555D SE555DR SE555JG SE555FK TOP-SIDE MARKING NE555P NE555 N555 N555 SA555P SA555 SE555P SE555D SE555JG
SE555FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE RESET Low High High TRIGGER VOLTAGE Irrelevant 1/3 VDD THRESHOLD VOLTAGE Irrelevant Irrelevant >2/3 VDD OUTPUT Low High Low DISCHARGE SWITCH On Off On
High >1/3 VDD <2/3 VDD Voltage levels shown are nominal.
As previously established
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
NE555, SA555, SE555 PRECISION TIMERS
SLFS022D SEPTEMBER 1973 REVISED JUNE 2003
functional block diagram
VCC 8 CONT 5 6 THRES RESET 4
R1 R S 1
2 TRIG
1 GND Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: RESET can override TRIG, which can override THRES.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Input voltage (CONT, RESET, THRES, and TRIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC Output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±225 mA Package thermal impedance, JA (see Notes 2 and 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85°C/W PS package . . . . . . . . . . . . . . . . . . . . . . . . . . . 95°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W Package thermal impedance, JC (see Notes 4 and 5): FK package . . . . . . . . . . . . . . . . . . . . . . . . . 5.61°C/W JG package . . . . . . . . . . . . . . . . . . . . . . . . . 14.5°C/W Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, P, PS, or PW package . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package . . . . . . . . . . . . . . . . . . . . 300°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND. 2. Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) TA)/JA. Operating at the absolute maximum TJ of 150°C can affect reliability. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. Maximum power dissipation is a function of TJ(max), JC, and TC. The maximum allowable power dissipation at any allowable case temperature is PD = (TJ(max) TC)/JC. Operating at the absolute maximum TJ of 150°C can affect reliability. 5. The package thermal impedance is calculated in accordance with MIL-STD-883.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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