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Part: PCM56U
Category:
Data Conversion
-> DAC (Digital to Analog Converters)
-> Audio DACs
Description: ti PCM56, Series Input 16-Bit Monolithic Digital-to-analog Converter
Company: Texas Instruments, Inc.
Datasheet: Download PCM56U datasheet File size : 566 kB
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Datasheet text preview:
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PCM56P PCM56U
DESIGNED FOR AUDIO
Serial Input 16-Bit Monolithic DIGITAL-TO-ANALOG CONVERTER
FEATURES
q SERIAL INPUT q 92dB MAX THD: FS Input, K Grade q 74dB MAX THD: 20dB Input, K Grade q q q q q q q q q q 96dB DYNAMIC RANGE NO EXTERNAL COMPONENTS REQUIRED 16-BIT RESOLUTION 15-BIT MONOTONICITY, TYP 0.001% OF FSR TYP DIFFERENTIAL LINEARITY ERROR 1.5µs SETTLING TIME, TYP: Voltage Out ±3V OR ±1mA AUDIO OUTPUT EIAJ STC-007-COMPATIBLE OPERATES ON ±5V TO ±12V SUPPLIES PINOUT ALLOWS IOUT OPTION This converter is completely self-contained with a stable, low noise, internal zener voltage reference; high speed current switches; a resistor ladder network; and a fast settling, low noise output operational amplifier all on a single monolithic chip. The converters are operated using two power supplies that can range from ±5V to ±12V. Power dissipation with ±5V supplies is typically less than 200mW. Also included is a provision for external adjustment of the MSB error (differential linearity error at bipolar zero) to further improve total harmonic distortion (THD) specifications if desired. Few external components a r e necessary for operation, and all critical specifications are 100% tested. This helps assure the user of high system reliability and outstanding overall system performance. The PCM56 is packaged in a high-quality 16-pin molded plastic DIP package or SOIC and has passed operating life tests under simultaneous high-pressure, high-temperature, and high-humidity conditions.
q PLASTIC DIP OR SOIC PACKAGE
DESCRIPTION
The PCM56 is a state-of-the-art, fully monotonic, digital-to-analog converter that is designed and specified for digital audio applications. This device employs ultra-stable nichrome (NiCr) thin-film resistors to provide monotonicity, low distortion, and low differential linearity error (especially around bipolar zero) over long periods of time and over the full operating temperature.
Reference I 16-Bit OUT DAC
RF
16-Bit Input Latch
O udio A utput
16-Bit Serial-to-Parallel Conversion Clock LE Data
International Airport Industrial Park · Mailing Address: PO Box 11400 · Tucson, AZ 85734 · Street Address: 6730 S. Tucson Blvd. · Tucson, AZ 85706 Tel: (520) 746-1111 · Twx: 910-952-1111 · Cable: BBRCORP · Telex: 066-6491 · FAX: (520) 889-1510 · Immediate Product Info: (800) 548-6132
©
1987 Burr-Brown Corporation
PDS-700D
Printed in U.S.A. August, 1993
SBAS149
SPECIFICATIONS
ELECTRICAL
Typical at +25°C, and nominal power supply voltages ±5V, unless otherwise noted. PCM56U, PCM56P-J, -K PARAMETER DIGITAL INPUT Resolution Digital Inputs(1): VIH VIL IIH, VIN = +2.7V IIL, VIN = +0.4V Input Clock Frequency TRANSFER CHARACTERISTICS ACCURACY Gain Error Bipolar Zero Error Differential Linearity Error Noise (rms, 20Hz to 20kHz) at Bipolar Zero (VOUT models) TOTAL HARMONIC DISTORTION VO = ±FS at f = 991Hz: PCM56P-K PCM56P-J PCM56P, PCM56U PCM56P-L VO = 20dB at f = 991Hz: PCM56P-K PCM56P-J PCM56P, PCM56U PCM56P-L VO = 60dB at f = 991Hz: PCM56P-K PCM56P-J PCM56P, PCM56U PCM56P-L MONOTONICITY DRIFT (0°C to +70°C) Total Drift(3) Bipolar Zero Drift SETTLING TIME (to ±0.006% of FSR) Voltage Output: 6V Step 1LSB Slew Rate Current Output, 1mA Step: 10 to 100 Load 1k Load(4) WARM-UP TIME OUTPUT Voltage Output Configuration: Bipolar Range Output Current Output Impedance Short Circuit Duration Current Output Configuration: Bipolar Range (±30%) Output Impedance (±30%) POWER SUPPLY REQUIREMENTS(5) Voltage: +VS and +VL VS and VL Supply Drain (No Load): +V (+VS and +VL = +5V) V (VS and VL = 5V) +V (+VS and +VL = +12V) V (VS and VL = 12V) Power Dissipation: VS and VL = ±5V VS and VL = ±12V TEMPERATURE RANGE Specification Operation Storage 1 ±3.0 0.10 Indefinite to Common ±1.0 1.2 +4.75 4.75 +5.00 5.00 +10.00 25.0 +12.0 27.0 175 468 +13.2 13.2 +17.0 35.0 MIN TYP 16 +2.4 0 +VL +0.8 +1.0 50 MAX UNITS Bits V V µA µA MHz
10.0
±2.0 ±30 ±0.001 6 94 94 94 94 75 75 75 75 35 35 35 35 15 ±25 ±4 1.5 1.0 10 350 350 92 88 82 80 74 68 68 60 34 28 28 20
% mV % of FSR(2) µV dB dB dB dB dB dB dB dB dB dB dB dB Bits ppm of FSR/°C ppm of FSR/°C µs µs V/µs ns ns M in V mA
±2.0
mA k V V mA mA mA mA mW mW °C °C °C
260
0 25 60
+70 +70 +100
NOTES: (1) Logic input levels are TTL/CMOS-compatible. (2) FSR means full-scale range and is equivalent to 6V (±3V) for PCM56 in the VOUT mode. (3) This is the combined drift error due to gain, offset, and linearity over temperature. (4) Measured with an active clamp to provide a low impedance for approximately 200ns. (5) All specifications assume +VS connected to +VL and VS connected to VL. If supplies are connected separately, VL must not be more negative than VS supply voltage to assure proper operation. No similar restriction applies to the value of +VL with respect to +VS.
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PCM56
2
ABSOLUTE MAXIMUM RATINGS
DC Supply Voltages .... ±16VDC Input Logic Voltage ... 1V to +VS/+VL Power Dissipation ........ 850mW Operating Temperature ..... 25°C to +70°C Storage Temperature ...... 60°C to +100°C Lead Temperature (soldering, 10s) ...... +300°C
PACKAGE INFORMATION
MODEL PCM56U PCM56P PCM56P-J PCM56P-K PCM56P-L PACKAGE 16-Pin SOIC 16-Pin Plastic DIP 16-Pin Plastic DIP 16-Pin Plastic DIP 16-Pin Plastic DIP PACKAGE DRAWING NUMBER(1) 211 180 180 180 180
PIN ASSIGNMENTS
PIN P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 DESCRIPTION Analog Negative Supply Logic Common Logic Positive Supply No Connection Clock Input Latch Enable Input Serial Data Input Logic Negative Supply Voltage Output Feedback Resistor Summing Junction Analog Common Current Output MSB Adjustment Terminal MSB Trim-pot Terminal Analog Positive Supply MNEMONIC VS LOG COM +VL NC CLK LE DATA VL VOUT RF SJ ANA COM IOUT MSB ADJ TRIM +VS
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book.
CONNECTION DIAGRAM
5V 1µF
VS C Logic ommon +VL
2 1 3
16 D 16-Bit AC Latch
VS
+5V 1µF
15 Trim(1) 16-Bit Serial to Parallel Conversion 1I6-Bit D UT O AC 14 MSB Adjust(1) 13 12 11 9 0 SJ RF Analog O utput
(
+5V 1µF
4 5 6 7 8
NC CLK LE Data 5V 1µF VL
IOUT C nalog A ommon
LControl ogic and SLevel C ifting h ircuit
VOUT ±3.0V)
NOTE: (1) MSB error (Bipolar Zero differential linearity error) can be adjusted to zero using the external circuit shown in Figure 6.
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PCM56
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