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Part: DIR1703
Category:
Description:
Company: Texas Instruments, Inc.
Datasheet: Download DIR1703 datasheet File size : 108 kB
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DIR1703
SLES007 JULY 2001
DIGITAL AUDIO INTERFACE RECEIVER
FEATURES D Standard Digital Audio Interface Receiver D D D D
(EIAJ1201) Sampling Rate: 32 / 44.1 / 48 / 88.2 / 96 kHz Recover 128 / 256 / 384 / 512 fs System Clock Very Low Jitter System Clock Output (75 ps Typically) On-Chip Master Clock Oscillator, Only an External Crystal Is Required: 24.576 / 22.5792 / 18.432 / 16.9344 / 16.384 / 12.288 / 11.2896 / 8.192 / 6.144 / 5.6448 / 4.096 MHz Crystals Are Available Selectable Output PCM Audio Data Format Selectable Crystal Clock and PPL Clock Operation Mode Output User Bit Data, Flag Signals, and Channel Status Data With Block Start Signal Single 3.3-V Power Supply Package: 28 SSOP
DESCRIPTION
The DIR1703 is a digital audio interface receiver (DIR) which receives and decodes audio data up to 96 kHz according to the AES/EBU, IEC958, S/PDIF, and EIAJCP340/1201 consumer and professional format interface standards. The DIR1703 demultiplexes the channel status bit and user bit directly to serial output pins, and has dedicated output pins for the most important channel status bits. It also includes extensive errors reporting. The significant advantages of the DIR1703 are 96-kHz sampling rate capability and Low-jitter clock recovery by the Sampling Period Adaptive Controlled Tracking (SpAct) system. The input signal is reclocked with the patented Sampling period Adaptive controlled tracking system for maximum quality. These features are required for recent consumer and professional audio instruments, in which the DIR has an interface to any kind of delta-sigma type ADC/DAC with a 96-kHz sampling rate.
D D D D D
APPLICATIONS D AV Receiver D MD Player D DAC Unit
This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SpAct and Burr-Brown are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2001, Texas Instruments Incorporated
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DIR1703
SLES007 JULY 2001
DIR1703 (TOP VIEW)
ADFLG BRATE0 BRATE1 SCKO VDD DGND XTO XTI CKTRNS LRCKO BCKO DOUT SCF0 SCF1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
CKSEL UNLOCK FMT1 FMT0 VCC AGND FILT RST DIN BRSEL BFRAME EMFLG URBIT CSBIT
PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER 324 OPERATION TEMPERATURE RANGE 25°C to +85°C to 85°C PACKAGE MARKING DIR1703E ORDERING NUMBER} DIR1703E TRANSPORT MEDIA Rails
DIR1703E/2K Tape and Reel TI equivalent no. 4040065. Models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of DIR1703E/2K will get a single 2000-piece tape and reel.
DIR1703E
SSOP28
block diagram
VDD XTI OSC XTO PLL1 OSC Selector Audio Clock And Data Generator PLL2 SCKO BCKO LRCKO DOUT BFRAME URBIT CSBIT EMFLG ADFLG rdclk VCC BRSEL SCF CKSEL FMT
100 MHZ DIN wrclk S/PDIF Decoder BRATE 2 FIFO SpAct
UNLOCK CKTRNS
FILT
RST
DGND
AGND
2
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DIR1703
SLES007 JULY 2001
Terminal Functions
TERMINAL NAME ADFLG BRATE0 BRATE1 SCKO VDD DGND XTO XTI CKTRNS LRCKO BCKO DOUT SCF0 SCF1 CSBIT URBIT EMFLG BFRAME BRSEL DIN RST FILT AGND VCC FMT0 FMT1 UNLOCK CKSEL NOTES: 1. 2. 3. 4. PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 I/O O O O O O I O O O O I I O O O O I I I I I O I Audio data or digital data flag fs rate flag 0 (32 k, 44.1 k, 48 k, and 88 k / 96 k) fs rate flag 1 (32 k, 44.1 k, 48 k, and 88 k / 96 k) System clock output Digital power supply, +3.3 V Digital ground Crystal oscillator output Crystal oscillator input, external clock input Clock transition status output Audio latch enable (LRCK, fs) output Audio bit clock output Audio serial data output System clock frequency select (128/256/384/512 fs) (see Note 1) System clock frequency select (128/256/384/512 fs) (see Note 1) Channel status bit output (see Note 2) User bit output (see Note 2) Emphasis flag Block start clock (B-frame) Default bit rate select (32 / 44.1 / 48 / 88.2 / 96 kHz) (see Note 1) S/PDIF data digital input (see Note 4) Reset input, active LOW (see Note 3) External filter Analog ground Analog power supply, 3.3V Audio data format select (see Note 1) Audio data format select (see Note 1) PLL unlock or parity error flag System clock operation mode selected. Low: PLL, High: Crystal (see Note 1) DESCRIPTIONS
Schmitt trigger input with internal pulldown (TYP 51 k), 5 V tolerant. Serial outputs are utilized for both consumer and professional application. Schmitt trigger input with internal pullup (TYP 51 k), 5 V tolerant. CMOS level input with internal pulldown (TYP 51 k), 5 V tolerant.
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DIR1703
SLES007 JULY 2001
absolute maximum ratings
Supply voltage, VCC, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V Supply voltage differences, VCC, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.1 V Ground voltage differences, AGND, DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.1 V Digital input voltage: Digital input pins except XTI . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to (6.5 V + 0.3 V) XTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to (VDD + 0.3 V) Input current (Any pins except supplies) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA Ambient temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 125°C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C to 150°C Junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Lead temperature (soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C, 5 sec Package temperature (IR reflow, peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235°C, 10 sec
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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DIR1703
SLES007 JULY 2001
electrical characteristics, all specifications at TA = 25°C, VCC = VDD = 3.3 V (unless otherwise noted)
PARAMETER DIGITAL INPUT/OUTPUT VIH (5) VIL (5) VIH2 (6) VIL2 (6) VIH3 (7) VIL3 (7) VOH (8) VOL (8) VOH (9) VOL (9) IIH(10) IIL(10) IIH(11) IIL(11) IIH(6) IIL(6) fs(12) SCKO tj Input sampling frequency System clock frequency SCKO clock jitter SCKO duty cycle XTI clock accuracy S/PDIF INPUT Duty cycle Jitter POWER SUPPLY REQUIREMENTS VDD, VCC ICC (VCC) IDD (VDD) PD Voltage range Supply current (see Note 13) current (see Note 13) Power dissipation Operation temperature JA NOTES: 5. 6. 7. 8. 9. 10. 11. 12. 13. Thermal resistance 28-pin SSOP 25 100 3 3.3 3.4 26 100 85 3.6 4.7 36 VDC mA mW °C °C/W VIN = 1.5 V, VIN = 1.5 V fs = 96 kHz 15% 85% ±10 ns p-p 500 TEST CONDITIONS MIN 2 70%VDD 30%VDD 70%VDD IO = 1 mA IO = 2 mA IO = 2 mA IO = 4 mA VIN = VDD VIN = 0 V Input leakage current leakage current VIN = VDD VIN = 0 V VIN = VDD VIN = 0 V VDD0.4 0.5 VDD0.4 0.5 65 10 10 100 10 10 32 4.096 128/256/ 384/512 fs 75 50% See Table 3 500 ppm 65 10 10 96 49.152 kHz MHz ps RMS 100 10 10 µA VDC 5.5 30%VDD TYP MAX 5.5 0.8 Input logic level logic level VDC UNIT
Output logic level logic level
TEMPERATURE RANGE
TTL compatible, except pins 8, 20: XTI, DIN. Pin 8: XTI (CMOS logic level). Pin 20: DIN (CMOS logic level). Pins 13, 9, 1718, 27: ADFLG, BRATE0, BRATE1, CKTRNS, EMFLG, BFRAME, UNLOCK. Pins 4, 1012, 1516: SCKO, LRCKO, BCKO, DOUT, CSBIT, URBIT. Pins 1314, 1920, 2526, 28: SCF0, SCF1, BRSEL, DIN, FMT0, FMT1, CKSEL. Pin 21: RST fs is defined as the incoming audio sampling frequency per channel. No load connected to SCKO, LRCKO, BCKO, DOUT, CSBIT, URBIT. Power supply current varies according to the system clock frequency.
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