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Part: S9418
Category:
Analog & Mixed-Signal Processing
-> Potentiometers
-> Nonvolatile DACPOT Potentiometer
Description: Quad 8-Bit Spi Compatible Nonvolatile DACPOT™ W/mute Pin
Company: Summit Microelectronics, Inc.
Datasheet: Download S9418 datasheet File size : 177 kB
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Datasheet text preview:
SUMMIT
M I C R O E L E C T R O N I C S , Inc.
S9418
Quad 8-Bit Nonvolatile DACPOTTM Electronic Potentiometer With a Mute Control Input
FEATURES · Four 8-Bit DACs -- Differential Non-linearity: ±0.5LSB max -- Integral Non-Linearity Error: ±1LSB max · Each DAC has Independent Reference Inputs -- Output Buffer Amplifiers Swing Rail-to-Rail -- Ground to VDD Reference Input Range · Each DAC's Digital Inputs Maintained in EEPROM · Power-On Reset Reloads Registers with Nonvolatile Data · Simple Serial Interface for Reading and Writing DAC values, SPITM and QSPITM compatible. · Fully operational from 2.7V to 5.5V · Low Power, 4mW max at +5V
OVERVIEW The S9418 DACPOTTM is a serial input, voltage output, quad 8-bit digital to analog converter (DAC). The S9418 operates from a single 2.7V to 5.5V supply. Internal precision buffers swing rail-to-rail and the reference input range includes both ground and the positive supply. The S9418 integrates four 8-bit DACs and their associated circuits which include; an enhanced unity gain operational amplifier output, an 8-bit data latch, an 8-bit nonvolatile register and an industry standard serial interface for reading and writing data to the DACs' data latches and registers. The DACs are independently programmable and each has its own electrically isolated Vreference inputs.
BLOCK DIAGRAM
Memory Control
8-Bit E2PROM DAC SECTION 0 2 VREFH0
VDD
3
Serial Data In 8-Bit Data Register 8-Bit DAC
AMP
18
VOUT0
RDY/BSY#
4
Programming Memory Controller
11 Serial Data Out 1 DAC SECTION 1 17 12
VREFL0
VREFH1 VOUT1 VREFL1
CS# DI CLK
6 7 5 Control Logic
20 MUTE 9 DAC SECTION 2 GND 10 16 13
VREFH2 VOUT2 VREFL2
19 DAC SECTION 3 15 14 8
SUMMIT MICROELECTRONICS, Inc. · 300 Orchard City Drive, Suite 131 · Campbell, CA 95008 · Telephone 408-378-6461 · Fax 408-378-6586 ·
VREFH3 VOUT3 VREFL3 DO
www.summitmicro.com
© SUMMIT MICROELECTRONICS, Inc. 2000 2023 2.2 8/2/00
1
Characteristics subject to change without notice
S9418
PINOUT and SIGNAL DEFINITION Pin 1, 2 19, 20
20-Pin PDIP or 20-Pin SOIC
Name VREFH VDD RDY/ BSY# CLK CS#
Function Vreference High: VREFH - VDD > VREFL Power Supply Voltage Ready/Busy#: open drain output indicating status of nonvolatile write operations Clock Input Pin: used for serial data communication Chip Select: When high deselects the device and places it in a low power mode Data Input: serial data input pin Data Output: serial data output pin When active forces VOUT to VREFL Power Supply Ground Vreference Low DAC Output: buffered D to A converter output
3 4
VREFH1 VREFH0 VDD RDY/BSY# CLK CS# DI DO MUTE GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VREFH2 VREFH3 VOUT0 VOUT1 VOUT2 VOUT3 VREFL3 VREFL2 VREFL1 VREFL0
2023 T PCon 2.0
5 6
7 8 9 10 11, 12 13, 14 15, 16 17, 18
DI DO MUTE GND V REFL V OUT
The analog outputs of the S9418 can be programmed to any one of 256 individual voltage steps. Each step value is 1/256th of the voltage differential between VREFH and VREFL of the respective DAC. Once programmed these settings can be retained in nonvolatile memory during all power conditions and will be automatically recalled upon a power-up sequence. Each DAC can be independently read without affecting the output voltage during the read cycle. In addition each output can be adjusted an unlimited number of times without altering the value stored in the nonvolatile memory. DEVICE OPERATION Analog Section The S9418 is an 8-bit, voltage output digital-to-analog converter (DAC). The DAC consists of a resistor network that converts 8-bit digital inputs into equivalent analog output voltages in proportion to the applied reference voltage. Reference inputs The voltage differential between the VREFL and VREFH inputs sets the full-scale output voltage for its respective DAC. VREFL must be equal to or greater than ground (positive voltage). VREFH must be greater (more positive) than VREFL or equal to VDD.
2023 2.2 8/2/00
Output Buffer Amplifiers The voltage outputs are from precision unity-gain followers that can slew up to 1V/µs. The outputs can swing from VREFL to VREFH. With a 0V to 5V output transition the amplifier outputs typically settle to 1LSB in 40µs. DIGITAL INTERFACE The S9418 employs a common 4-wire serial interface. It is comprised of a Clock (CLK), Chip Select (CS#), Data input (DI) and Data output (DO). Data is clocked into the device on the clock's rising edge and out of the device on the clock's falling edge. Data is shifted in and out MSB first. DO only becomes active after the device has been selected and after a valid read command and address has been received. All data transfers are initiated after CS# goes low and a logic `1' is clocked into the device. This first data transfer is the start bit and must precede all operations. Following the start bit are two command bits used to specify which of four commands to execute. The next two bits are the address bits used to select one of the four DACs. The action of the next eight clock cycles will be dependent upon the command issued.
2
S9418
Start 1 1 1 1 C1 0 0 1 1 C0 0 1 0 1 A1 A A A A A0 A A A A Command NV Write Enable Write -- Data In Read -- Data Out Recall
selected data register. This read will not affect the contents of the register or the output of the DAC. Refer to Figure 1 for an illustration of the sequence of bus conditions for a read operation. WRITE Write operations are initiated by taking CS# low and clocking in a start bit followed by the write command and the address of the data register to be written. This action is followed by the host clocking eight bits of data into the register, MSB first. The output of the selected DAC will change as the last bit is clocked into the device. At this point the clock counter will reset the command register, requiring a full sequence to be initiated in order to write to the DAC again. Refer to Figure 2 for an illustration of the sequence of bus conditions for a write operation.
TABLE 1. Internally there are four DACs and associated with each are two registers. There is one data register that is used by the DAC to hold the digital value it converts. There is also one nonvolatile register that holds the default value that can be recalled into the data register during powerup or by executing the Recall command. READ Read operations are initiated by taking CS# low and clocking in a start bit followed by the read command and the address of the data register to be read. The next eight clocks will output on the DO pin the contents of the
NOTE: This write operation does not affect the contents of the nonvolatile register. Therefore, the nonvolatile register can contain the power-on default settings (e.g. volume), and the write DAC command can be used to make situational adjustments.
CS# CLK
DI
S T A R T
C1
C0
A1
A0
DO
Hi Z
D7
D6
D5
D4
D3
D2
D1
D0
Hi Z
(Pulled up to VDD)
RDY/BSY#
2023 T fig01 2.0
FIGURE 1. READ SEQUENCE
2023 2.2 8/2/00
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