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Part: S42WD42
Category:
Power Management
-> Supervisory Circuits
-> Sequencers Supervisory
Description: Precision Voltage Supervisory Circuit With Watchdog Timer And 4k I2C™ Memory
Company: Summit Microelectronics, Inc.
Datasheet: Download S42WD42 datasheet File size : 589 kB
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Datasheet text preview:
S4242/S42WD42/S4261/S42WD61
Dual Voltage Supervisory Circuit With Watchdog Timer(S42WD61) (S42WD42)
FEATURES · Precision Dual Voltage Monitor VCC Supply Monitor - Dual reset outputs for complex microcontroller systems - Integrated memory write lockout function - No external components required · Second Voltage Monitor Output Separate VLOW output Generates interrupt to MCU Generates RESET for dual supply systems - Guaranteed output assertion to VCC - 1V · Watchdog Timer (S42WD42, S42WD61) 1.6s · Memory Internally Organized 2 x8 · Extended Programmable Functions Available on SMS24 · High Reliability Endurance: 100,000 erase/write cycles Data retention: 100 years OVERVIEW The S42xxx are a precision power supervisory circuit. It automatically monitors the device's VCC level and will generate a reset output on two complementary open drain outputs. In addition to the VCC monitoring, the S42xxx also provides a second voltage comparator input. This input has an independent open drain output that can be wireOR'ed with the RESET I/O or it can be used as a system interrupt. The S42xxx also has an integrated 4k/16k-bit nonvolatile memory. The memory conforms to the industry standard two-wire serial interface. In addition to the reset circuitry, the S42WD42/S42WD61 also has a watchdog timer.
BLOCK DIAGRAM
VCC 8
SCL SDA
6 5
NONVOLATILE MEMORY ARRAY
WRITE CONTROL
PROGRAMMABLE RESET PULSE GENERATOR
2
RESET#
+
VTRIP
RESET CONTROL
7 PROGRAMMABLE WATCHDOG TIMER (S42WD42, S42WD61) 1 UV VSENSE 3 + OV 1.26V 4 GND
2025 T BD 2.0
RESET
VLOW#
SUMMIT MICROELECTRONICS, Inc.
·
300 Orchard City Drive, Suite 131
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Campbell, CA 95008
·
Telephone 408-378-6461
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Fax 408-378-6586
·
www.summitmicro.com
© SUMMIT MICROELECTRONICS, Inc. 2000 2025 6.0 4/17/00
Characteristics subject to change without notice
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S4242/S42WD42/S4261/S42WD61
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ............. -40°C to +85°C Storage Temperature .... -65°C to +125°C Soldering Temperature (less than 10 seconds) .......... 300°C Supply Voltage .... 0 to 6.5V Voltage on Any Pin ...... -0.3V to VCC+0.3V ESD Voltage (JEDEC method) ......... 2,000V
NOTE: These are STRESS ratings only. Appropriate conditions for operating these devices are given elsewhere in this specification. Stresses beyond those listed here may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature Commercial Industrial Min 0°C -40°C Max +70°C +85°C
2025 PGM T1.0
DC ELECTRICAL CHARACTERISTICS (over recommended operating conditions unless otherwise specified)
Symbol ICC I SB I LI I LO V IL VIH V OL Parameter Supply Current (CMOS) Standby Current (CMOS) Input Leakage Output Leakage Input Low Voltage Input High Voltage Output Low Voltage Conditions SCL = CMOS Levels @ 100KHz SDA = Open All other inputs = GND or VCC SCL = SDA = VCC All other inputs = GND VIN = 0 To VCC VOUT = 0 To VCC SCL, SDA, RESET# (pin 2) SCL, SDA, RESET (pin7) IOL = 3mA SDA VCC =5.5V VCC =3.3V VCC =5.5V VCC =3.3V Min Max 3 2 50 25 10 10 0.3xVCC 0.7xVCC 0.4 Units mA mA µA µA µA µA V V V
2025 PGM T2.0
AC ELECTRICAL CHARACTERISTICS (over recommended operating conditions unless otherwise specified)
Symbol Parameter SCL Clock Frequency Clock Low Period Clock High Period Bus Free Time Start Condition Setup Time Start Condition Hold Time Stop Condition Setup Time Clock to Output Data Out Hold Time SCL and SDA Rise Time SCL and SDA Fall Time Data In Setup Time Data In Hold Time Noise Spike Width @ SCL, SDA Inputs Write Cycle Time Noise Suppression Time Constant SCL Low to SDA Data Out Valid SCL Low to SDA Data Out Change Before New Transmission Conditions
2.7V to 4.5V Min 0 4.7 4.0 4.7 4.7 4.0 4.7 0.3 0.3 1000 300 250 0 100 10 3.5 Max 100
4.5V to 5.5V Min Max 400 1.3 0.6 1.3 0.6 0.6 0.6 0.2 0.2 300 300 100 0 100 10 0.9 Units KHz µs µs µs µs µs µs µs µs ns ns ns ns ns ms
2025 PGM T3.0
fSCL t LOW tHIGH tBUF tSU:STA tHD:STA tSU:STO tA A tDH tR tF tSU:DAT tHD:DAT
TI
tWR
2025 6.0 4/17/00
2
S4242/S42WD42/S4261/S42WD61
CAPACITANCE TA = 25°C, f = 100KHz Symbol CIN COUT Parameter Input Capacitance Output Capacitance Max 5 8 Units pF pF
2025 PGM T4.0
tR
tF
tHIGH
tLOW
SCL
tSU:SDA tHD:DAT tSU:DAT tSU:STO
tHD:SDA
tBUF
SDA In
tAA
tDH
SDA Out
2025 Fig01 1.0
FIGURE 1. BUS TIMING
START Condition SCL
STOP Condition
SDA In
2025 Fig02 1.0
FIGURE 2. START AND STOP CONDITIONS
2025 6.0 4/17/00
3
Others parts begin by s4
S4-1 S4-2 S4-3
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