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Part: M29W040-150N1R
Category:
Memory
-> Flash
Description: 4 Mbit 512kb X8, Uniform Block Low Voltage Single Supply Flash Memory
Company: ST Microelectronics, Inc.
Datasheet: Download M29W040-150N1R datasheet File size : 473 kB
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Datasheet text preview:
M29W040
4 Mbit (512Kb x8, Uniform Block) Low Voltage Single Supply Flash Memory
N OT FOR NEW DESIGN
M29W040 is replaced by the M29W040B 2.7V to 3.6V SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS FAST ACCESS TIME: 100ns BYTE PROGRAMMING TIME: 12µs typical ERASE TIME Block: 1.5 sec typical Chip: 2.5 sec typical PROGRAM/ERASE CONTROLLER (P/E.C.) Program Byte-by-Byte Data Polling and Toggle bits Protocol for P/E.C. Status MEMORY ERASE in BLOCKS 8 Uniform Blocks of 64 KBytes each Block Protection Multiblock Erase ERASE SUSPEND and RESUME MODES LOW POWER CONSUMPTION Read mode: 8mA typical (at 12MHz) Stand-by mode: 20µA typical Automatic Stand-by mode POWER DOWN SOFTWARE COMMAND Power-down mode: 1µA typical 100,000 PROGRAM/ERASE CYCLES per BLOCK 20 YEARS DATA RETENTION Defectivity below 1ppm/year ELECTRONIC SIGNATURE Manufacturer Code: 20h Device Code: E3h Table 1. Signal Names
A0-A18 DQ0-DQ7 E G W VCC VSS Address Inputs Data Input / Outputs Chip Enable Output Enable Write Enable Supply Voltage Ground
PLCC32 (K)
TSOP32 ( N) 8 x 20mm
TSOP32 ( NZ) 8 x 14mm
Figure 1. Logic Diagram
VCC
19 A0-A18
8 DQ0-DQ7
W E G
M29W040
VSS
AI02074
N ovember 1999
This is information o n a product still in product ion but not recommende d for new designs.
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M29W040
F igure 2A. LCC Pin Connections Figure 2B. TSOP Pin Connections
1 32 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 A14 A13 A8 A9 A11 G A10 E DQ7
9
M29W040
25
17 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6
AI02075
A11 A9 A8 A13 A14 A17 W VCC A18 A16 A15 A12 A7 A6 A5 A4
A 12 A 15 A 16 A 18 V CC W A 17
1
32
8 9
M29W040 (Normal)
25 24
16
17
AI02076
G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
F igure 2C. TSOP Reverse Pin Connections
G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
1
32
8 9
M29W040 (Reverse)
25 24
16
17
AI02077
A11 A9 A8 A13 A14 A17 W VCC A18 A16 A15 A12 A7 A6 A5 A4
DESCRIPTION The M29W040 is a non-volatile memory that may be erased electrically at the block level, and programmed Byte-by-Byte. The interface is directly compatible with most microprocessors. PLCC32, TSOP32 (8 x 20mm) and TSOP32 (8 x 14mm) packages are available. Both normal and reverse pin outs are available for t he TSOP32 (8 x 20mm) package. Organisation The Flash Memory organisation is 512K x8 bits with Address lines A0-A18 and Data Inputs/Outpu ts DQ0-DQ7. Memory control is provided by Chip Enable, Output Enable and Write Enable Inputs. Erase and Program are performed through the internal Program/Erase Controller (P/E.C.). Data Outputs bits DQ7 and DQ6 provide polling or toggle signals during Automatic Program or Erase to in dicate the Ready/Busy state of the internal Program/Erase Controller. Memory Blocks Erasure of the memory is in blocks. There are 8 uniform blocks of 64 Kbytes each in the memory address space. Each block can be programmed and erased over 100,000 cycles. Each uniform
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M29W040
Table 2. Absolute Maximum Ratings ( 1)
Symbol TA TBIAS TSTG VIO
(2)
Parameter Ambient Operating Temperature Temperature Under Bias Storage Temperature Input or O utput Voltages Supply Voltage A9 Voltage
(3)
Value 40 to 85 50 to 125 65 to 150 0.6 to 5 0.6 to 5 0.6 to 13.5
Unit °C °C °C V V V
VC C VA9
(2)
N otes: 1. Except for the r ating "Operating Temperature Range", stresses above those listed in t he Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are s tress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not i mplied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. R efer als o to the S TMicroelectronics SURE Program and other relevant quality documents. 2. Minimum Voltage may undershoot t o 2V during transition and for less than 20ns. 3. Depends on range.
block may separately be protected and unprot ected against program and erase. Block erasure may be suspended, while data is read from other blocks of the memory, and then resumed. Bus Operations Seven operations can be performed by the appropriate bus cycles, Read Array, Read Electronic Signature, Output Disable, Standby, Protect Block, Unprotect Block, and Write the Command of an I nstruction. Command Interface Command Bytes can be written to a Command I nterface (C.I.) latch to perform Reading (from the Array or Electronic Signature), Erasure or Programming. For added data protection, command execution starts after 4 or 6 command cycles. The f irst, second, f ourth and fifth cycles are used t o input a code sequence t o the Command Interface (C.I.). This sequence is equal for all P/E.C. instruct ions. Command itself and its confirmation - if it applies - are given on the third and fourth or sixth cycles. I nstructions Eight instructions are defined to perform Reset, Read Electronic Signature, Auto Program, Block Auto Erase, Chip Auto Erase, Block Erase Suspend, Block Erase Resume and Power Down. The internal Program/Erase Controller (P/E.C.) handles all timing and verification of the Program and Erase
instructions and provides Data Polling, Toggle, and Status data t o indicate completion of Program and Erase Operations. Instructions are composed of up to six cycles. The first two cycles input a code sequenc e to the Command Interface which is common to all P/E.C. instructions (see Table 7 for Command Descriptions). The third cycle inputs the instruction set up command instruction t o the Command I nterface. Subseq uent cycles output Signature, Block Protection or the addressed data f or Read operations. For added data protection, the instructions for program, and block or chip erase require further command inputs. For a Program instruction, the fourth command cycle inputs the address and data to be programmed. For an Erase instruction (block or chip), the fourth and fifth cycles input a further code sequenc e before the Erase confirm command on the sixth cycle. Byte programming takes t ypically 12µs while erase is performed in typically 1.5 second. Erasure of a memory block may be suspend ed, in order to read data from another block, and then resumed. Data Polling, Toggle and Error data may be read at any time, including during the programming or erase cycles, to monitor the progress of the operation. When power is first applied or if VCC falls b elow VLKO , t he command interface is reset to Read Array.
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