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Part: M29W004T-90N6TR
Category:
Memory
-> Flash
Description: 4 Mbit 512kb X8, Boot Block Low Voltage Single Supply Flash Memory
Company: ST Microelectronics, Inc.
Datasheet: Download M29W004T-90N6TR datasheet File size : 1053 kB
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Datasheet text preview:
M29W004T M29W004B
4 Mbit (512Kb x8, Boot Block) Low Voltage Single Supply Flash Memory
NOT FOR NEW DESIGN
M29W004T and M29W004B are replaced respectively by the M29W004BT and M29W004BB 2.7 to 3.6V SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS FAST ACCESS TIME: 100ns FAST PROGRAMMING TIME: 10µs typical PROGRAM/ERASE CONTROLLER (P/E.C.) Program Byte-by-Byte Status Register bits and Ready/Busy Output MEMORY BLOCKS Boot Block (Top or Bottom location) Parameter and Main blocks BLOCK, MULTI-BLOCK and CHIP ERASE MULTI BLOCK PROTECTION/TEMPORARY UNPROTECTION MODES ERASE SUSPEND and RESUME MODES Read and Program another Block during Erase Suspend LOW POWER CONSUMPTION Stand-by and Automatic Stand-by 100,000 PROGRAM/ERASE CYCLES per BLOCK 20 YEARS DATA RETENTION Defectivity below 1ppm/year ELECTRONIC SIGNATURE Manufacturer Code: 20h Device Code, M29W004T: EAh Device Code, M29W004B: EBh DESCRIPTION The M29W004 is a non-volatile memory that may be erased electrically at the block or chip level and programmed in-system on a Byte-by-Byte basis using only a single 2.7V to 3.6V VCC supply. For Program and Erase operations the necessary high voltages are generated internally. The device can also be programmed in standard programmers. The array matrix organisation allows each block to be erased and reprogrammed without affecting other blocks. Blocks can be protected against programing and erase on programming equipment, and temporarily unprotected to make changes in
June 1999
TSOP40 (N) 10 x 20 mm
Figure 1. Logic Diagram
VCC
19 A0-A18 W E G RP M29W004T M29W004B
8 DQ0-DQ7
RB
VSS
AI02063
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This is information on a product still in production but not recommended for new designs.
M29W004T, M29W004B
Figure 2. TSOP Pin Connections
A16 A15 A14 A13 A12 A11 A9 A8 W RP NC RB A18 A7 A6 A5 A4 A3 A2 A1 1 40 A17 VSS NC NC A10 DQ7 DQ6 DQ5 DQ4 VCC VCC NC DQ3 DQ2 DQ1 DQ0 G VSS E A0
Table 1. Signal Names
A0-A18 DQ0-DQ7 E G W RP RB VCC VSS Address Inputs Data Input/Outputs, Command Inputs Chip Enable Output Enable Write Enable Reset / Block Temporary Unprotect Ready/Busy Output Supply Voltage Ground
10 11
M29W004T M29W004B
31 30
cycles of commands to a Command Interface using standard microprocessor write timings. The device is offered in TSOP40 (10 x 20mm) package. Organisation The M29W004 is organised as 512K x8. The memory uses the address inputs A0-A18 and the Data Input/Outputs DQ0-DQ7. Memory control is provided by Chip Enable E, Output Enable G and Write Enable W inputs. A Reset/Block Temporary Unprotection RP tri-level input provides a hardware reset when pulled Low, and when held High (at VID) temporarily unprotects blocks previously protected allowing them to be programed and erased. Erase and Program operations are controlled by an internal Program/Erase Controller (P/E.C.). Status Register data output on DQ7 provides a Data Polling signal, and DQ6 and DQ2 provide Toggle signals to indicate the state of the P/E.C operations. A Ready/Busy RB output indicates the completion of the internal algorithms.
20
21
AI02064
Warning: NC = Not Connected.
DESCRIPTION (Cont'd) the application. Each block can be programmed and erased over 100,000 cycles. Instructions for Read/Reset, Auto Select for reading the Electronic Signature or Block Protection status, Programming, Block and Chip Erase, Erase Suspend and Resume are written to the device in Table 2. Absolute Maximum Ratings (1)
Symbol TA TBIAS TSTG VIO
(2)
Parameter Ambient Operating Temperature Temperature Under Bias Storage Temperature Input or Output Voltages Supply Voltage
(2) (3)
Value 40 to 85 50 to 125 65 to 150 0.6 to 5 0.6 to 5 0.6 to 13.5
Unit °C °C °C V V V
VCC V(A9, E, G, RP)
A9, E, G, RP Voltage
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum Voltage may undershoot to 2V during transition and for less than 20ns. 3. Depends on range.
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M29W004T, M29W004B
Memory Blocks The devices feature asymmetrically blocked architecture providing system memory integration. Both M29W004T and M29W004B devices have an array of 11 blocks, one Boot Block of 16K Bytes, two Parameter Blocks of 8K Bytes, one Main Block of 32K Bytes and seven Main Blocks of 64K Bytes. The M29W004T has the Boot Block at the top of the memory address space and the M29W004B locates the Boot Block starting at the bottom. The memory maps are showed in Figure 3. Each block can be erased separately, any combination of blocks can be specified for multi-block erase or the entire chip may be erased. The Erase operations are managed automatically by the P/E.C. The block erase operation can be suspended in order to read from or program to any block not being ersased, and then resumed. Block protection provides additional data security. Each block can be separately protected or unprotected against Program or Erase on programming equipment. All previously protected blocks can be temporarily unprotected in the application. Bus Operations The following operations can be performed using the appropriate bus cycles: Read (Array, Electronic Signature, Block Protection Status), Write command, Output Disable, Standby, Reset, Block Prot e c t i o n , U n p r o t e c t i o n , Pro t e c t i o n Ve r i f y, Unprotection Verify and Block Temporary Unprotection. See Tables 4 and 5. Command Interface Instructions, made up of commands written in cycles, can be given to the Program/Erase Controller through a Command Interface (C.I.). For added data protection, program or erase execution starts after 4 or 6 cycles. The first, second, fourth and fifth cycles are used to input Coded cycles to the C.I. This Coded sequence is the same for all Program/Erase Controller instructions. The 'Command' itself and its confirmation, when applicable, are given on the third, fourth or sixth cycles. Any incorrect command or any improper command sequence will reset the device to Read Array mode. Instructions Seven instructions are defined to perform Read Array, Auto Select (to read the Electronic Signature or Block Protection Status), Program, Block Erase, Chip Erase, Erase Suspend and Erase Resume. The internal P/E.C. automatically handles all timing and verification of the Program and Erase operations. The Status Register Data Polling, Toggle, Error bits and the RB output may be read at any time, during programming or erase, to monitor the progress of the operation. Instructions are composed of up to six cycles. The first two cycles input a Coded sequence to the Command Interface which is common to all instructions (see Table 8). The third cycle inputs the instruction set-up command. Subsequent cycles output the addressed data, Electronic Signature or Block Protection Status for Read operations. In order to give additional data protection, the instructions for Program and Block or Chip Erase require further command inputs. For a Program instruction, the fourth command cycle inputs the address and data to be programmed. For an Erase instruction (Block or Chip), the fourth and fifth cycles input a further Coded sequence before the Erase confirm command on the sixth cycle. Erasure of a memory block may be suspended, in order to read data from another block or to program data in another block, and then resumed. When power is first applied or if Vcc falls below VLKO, the command interface is reset to Read Array. SIGNAL DESCRIPTIONS See Figure 1 and Table 1. Address Inputs (A0-A18). The address inputs for the memory array are latched during a write operation on the falling edge of Chip Enable E or Write Enable W. In Word-wide organisation the address lines are A0-A18. When A9 is raised to VID, either a Read Electronic Signature Manufacturer or Device Code, Block Protection Status or a Write Block Protection or Block Unprotection is enabled depending on the combination of levels on A0, A1, A6, A12 and A15. Data Input/Outputs (DQ0-DQ7). The input is data to be programmed in the memory array or a command to be written to the C.I. Both are latched on the rising edge of Chip Enable E or Write Enable W. The output is data from the Memory Array, the El e ct ro ni c Signature Manufacturer or Device codes, the Block Protection Status or the Status register Data Polling bit DQ7, the Toggle Bits DQ6 and DQ2, the Error bit DQ5 or the Erase Timer bit DQ3. Outputs are valid when Chip Enable E and Output Enable G are active. The output is high impedance when the chip is deselected or the outputs are disabled and when RP is at a Low level. Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. E High deselects the memory and reduces the power consumption to the standby level. E can also be used to control writing to the command register and to the memory array, while W remains at a low level. The Chip Enable must be forced to VID during the Block Unprotection operation.
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