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Part: M295V100B-B90M6T
Category:
Memory
-> Flash
Description: 1 Mbit 128kb x8 or 64kb X16, Boot Block Single Supply Flash Memory
Company: ST Microelectronics, Inc.
Datasheet: Download M295V100B-B90M6T datasheet File size : 1053 kB
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Datasheet text preview:
M29F100BT M29F100BB
1 Mbit (12 8Kb x8 or 64K b x16, Boot Blo ck) Singl e Supply Flash Memory
PR ELIM INARY DATA
s
SING LE 5V±10% SUPPLY VOLTAGE for PROG RAM, ERASE and READ OPERATIONS ACCESS TIME: 45ns PROG RAMMING TIME 8µs per Byte/Word typical 5 MEMORY BLOCKS 1 Boot Block (Top or Bottom Location) 2 Parameter and 2 Main Blocks
1 44
s s
s
s
PROG RAM/ERASE CONTROLLER Embedded Byte/Word Program algorithm Embedded Multi-Block/Chip Erase algorithm Status Register Polling and Toggle Bits Ready/Busy Output Pin
TSOP 48 (N) 12 x 20mm
SO 44 (M)
s
ERASE SUSPEND and RESUME MODES Read and Program another Block during Erase Suspend
Figure 1. Logic Diagram
s
UNLOCK BYPASS PROGRAM COMMAND F aster Production/Batch Programming TEMPORARY BLOCK UNPROTECTION MODE LOW PO WER CONSUMPTION Standby and Automatic Standby 100,000 PROGRAM/ERASE CYCLES per BLOCK 20 YEARS DATA RETENTION Defectivity below 1 ppm/year ELECTRONIC SIGNATURE M anufacturer Code: 0020h M 29F100BT Device Code: 00D0h M 29F100BB Device Code: 00D1h
A0-A15 W E G RP
VCC
s
16
15 DQ0-DQ14 DQ15A1 M29F100BT M29F100BB BYTE RB
s
s
s
s
VSS
AI02916
July 1999
This is preliminary information on a new product now i n d evelopment or undergoing e valuation. D etails are subject to change without notice.
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M29F100BT, M 29F10 0 BB
Figure 2A. TSOP Connections
A15 A14 A13 A12 A11 A10 A9 A8 NC NC W RP NC NC RB NC NC A7 A6 A5 A4 A3 A2 A1 1 48 NC BYTE VSS DQ15A1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0
Figure 2B. SO Connections
12 13
M29F100BT M29F100BB
37 36
NC RB NC A7 A6 A5 A4 A3 A2 A1 A0 E VSS G DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11
1 2 3 4 5 6 7 8 9 10 11 M29F100BT 12 M29F100BB 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
RP W A8 A9 A10 A11 A12 A13 A14 A15 NC BYTE VSS DQ15A1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC
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AI02917
AI02918
Table 1. Signal Names
A0-A15 DQ0-DQ7 DQ8-DQ1 4 DQ15A1 E G W RP RB BYTE VCC VSS NC 2/21 Address Inputs Dat a Inputs/Outputs Dat a Inputs/Outputs Dat a Input/Output or Address I nput Chip Enable Out put E nable Wr ite E nable Reset/Block Temporary Unprotec t Ready/Busy O utput Byte /Word Organization S elect Supply Voltage Gro und Not Connected Inte rnally
SUMMARY DESCRIPTION The M29F100B is a 1 Mbit (128Kb x8 or 64Kb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single 5V supply. On power-up the memory defaults to its Read mode where it can be read in t he same way as a RO M or EPROM. The M29F100B i s fully backward compatible wit h the M29F100. The memory is divided i nto blocks that can be erased independently s o i t i s possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from m odifying t he memory. Program and Erase commands are written to the Command Interface of the m emory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required t o update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The c ommand set required to control t he memory is consistent with JEDEC standards.
M 29F1 00B T , M 29F10 0B B
Table 2. Absolute Maximum Ratings (1)
Symbol Parameter Ambient Operating Temperature (Temperature Range Op tion 1) TA Ambient Operating Temperature (Temperature Range Op tion 6) Ambient Operating Temperature (Temperature Range Op tion 3) TB IAS TSTG VIO (2) VCC VID Temperature Under Bias Storage Temperature Input or Outpu t Voltage Supply Voltage Identificat ion Voltage Value 0 to 70 40 to 85 40 to 125 50 to 125 65 to 150 0.6 to 6 0.6 to 6 0.6 to 13. 5 Unit °C °C °C °C °C V V V
Note: 1. Except f or th e rating "O perating Temperature Range", s tresses above those liste d in the Table "Absolute Maximum R atings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above t hose i ndicated in the O perating sections of this specification is not implied . Exposure to A bsolute M aximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelec tronics SURE Program and other relevant quality documents. 2. Minimum Voltag e may undershoot to 2V during tr ansition and for less than 20ns during transitions.
The blocks in the memory are asymmetrically arranged, see Tables 3A and 3B, Block Addresses. The first or last 64 Kbytes have been divided into four additional blocks. The 16 Kbyte Boot Block can be used for small initialization code to start the microprocessor, the two 8 Kbyte Parameter Blocks can be used for parameter storage and the remaining 32K is a small Main Block where the application may be stored. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow si mple connection to most microprocessors, often wit hout additional logic. The memory is offered in TSO P48 (12 x 20mm) and SO44 packages. Access times of 45ns, 70ns, 90ns and 120ns are available. The memory is supplied with all the bits erased (set to '1'). SIGNAL DESCRIPTIONS See Figure 1, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A15). T he Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control t he commands sent to the Command Interface of the internal sta te machine. Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent t he commands
sent to the Command Interface of the internal state machine. Data Inputs/Outputs (DQ8-DQ14). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading t he Status Register these bits should be ignored. Data Input/Output or Address Input (DQ15A-1). When BYTE is High, V IH, this pin behaves as a Data Input/Output pin (as DQ 8-DQ14). When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A1 Low will select the LSB of the Word on the other addresses, DQ15A1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address Inputs to include t his pin when BYTE is Low except when s tated explicitly otherwise. Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations t o be performed. When Chip Enable is High, VIH, all other pins are ignored. Output Enable (G). The Output Enable, G, c ontrols the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of th e memory's Command Interface.
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