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Part: M28C17A-20
Category:
Memory
-> ROM
-> EEPROM
-> Parallel
-> 16 Kb
Description: Obsolete - 16K (2K X8) Parallel EePROM
Company: ST Microelectronics, Inc.
Datasheet: Download M28C17A-20 datasheet File size : 24 kB
Request For quote: Find where to buy M28C17A-20
Datasheet text preview:
M28C16A M28C17A
16 Kbit (2Kb x8) Parallel EEPROM
FAST ACCESS TIME: 150ns at 5V 250ns at 3V SINGLE SUPPLY VOLTAGE: 5V ± 10% f or M28C16A and M28C17A 2.7V to 3.6V for M28C16-xxW LOW POWER CONSUMPTION FAST WRITE CYCLE 32 Bytes Page Write Operation Byte or Page Write Cycle: 5ms ENHANCED END OF WRITE DETECTION Ready/Busy Open Drain Output Data Polling Toggle Bit PAGE LOAD TIMER STATUS BIT HIGH RELIABILITY SINGLE POLYSILICON, CMOS TECHNOLOGY Endurance >100,000 Erase/Write Cycles Data Retention >40 Years JEDEC APPROVED BYTEWIDE PIN OUT DESCRIPTION The M28C16A and M28C17A are 2K x8 low power Parallel EEPROM fabricated with STMicroelectronics proprietary single polysilicon CMOS technology. The device offers fast access time with low power dissipation and requires a 5V or 3V power supply. Table 1 . Signal Names
A0-A10 DQ0-DQ7 W E G RB VCC VSS Address Input Data Input / Output Write Enable Chip Enable Output Enable Ready / Busy Supply Voltage Ground
28
1
PDIP28 (BS)
PLCC32 (KA)
28
1
SO28 (MS) 300 mils
T SOP28 (NS) 8 x13.4mm
Figure 1. Logic Diagram
VCC
11 A0-A10
8 DQ0-DQ7
W E
M28C16A M28C17A RB
G
VSS
AI02109
August 1998
1/19
M28C16A, M28C17A
Figure 2A. DIP Pin Connections Figure 2B. LCC Pin Connections
RB NC A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 6 7 M28C17A 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC W DU A8 A9 NC G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
A6 A5 A4 A3 A2 A1 A0 NC DQ0
RB or NC (1) DU V CC W DU 1 32 A8 A9 NC NC G A10 E DQ7 DQ6 M28C16A M28C17A 25 17
AI02111
9
AI02110
Warning: NC = Not Connected, D U = Don't Us e.
Warning: N C = Not Connected, DU = Don't Use. Note: 1. Pin 2 is either RB for M28C17A or N C for M 28C16A.
Figure 2C. SO Pin Connections
Figure 2D. TSOP Pin Connections
RB NC A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 6 7 M28C17A 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC W DU A8 A9 NC G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
G NC A9 A8 DU W VCC RB NC A7 A6 A5 A4 A3
22
DQ1 DQ2 VSS NC DQ3 DQ4 DQ5 21 28 1 M28C16A 15 14 7 8
AI02113
A7 NC
A10 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2
AI02112
Warning: NC = Not Connected, D U = Don't Us e. 2/19
Warning: N C = Not Connected, DU = Don't Use.
M28C16A, M28C17A
Table 2 . Absolute Maximum Ratings (1)
Symbol TA T STG VCC V IO VI VESD Parameter Ambient Operating Temperature Storage Temperature Range Supply Voltage Input/Output Voltage Input Voltage Electrostatic Discharge Voltage (Human Body model)
(2)
Value 40 to 85 65 to 150 0.3 to 6.5 0.3 to VCC +0.6 0.3 to 6.5 3000
Unit °C °C V V V V
Notes: 1. Except for the rating "Operating Temperature Range", s tresses above those lis ted in the Table "Absolute Maximum Ra tings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this s pecification is not i mplied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Depends on range.
Table 3 . Operating Modes
M ode Read Write Standby / Write Inhibit Write Inhibit Write Inhibit Output Disable
Note: X = VIH or VIL
E VIL VIL VIH X X X
G VIL VIH X X VIL VIH
W VIH VIL X VIH X X
D Q0 - DQ7 D ata Out Data In Hi-Z D ata Out or Hi-Z D ata Out or Hi-Z Hi-Z
DESCRIPTION (cont'd) The circuit has been designed t o offer a f lexible microcontroller interface featuring both hardware and software handshakin g mode with Ready/Busy, Data Polling and Toggle Bit. The M28C16A/17A supports 32 byte page write operation. PIN DESCRITPION Addresses (A0-A10). The address inputs select an 8-bit memory location during a read or write operation. Chip Enable (E). The chip enable input must be low to enable all read/write operations . When Chip Enable is high, power consumption is reduced. Output Enable (G). The Output Enable input controls the data output buffers and is used t o initiate read operations. Data In/ Out (DQ0 - DQ7). Data is written to or read from the M28C16A/17A through the I/O pins.
Write Enable (W). The Write Enable input controls the writing of data to the M28C16A/17A. Ready/Busy (RB). Ready/Busy is an open drain output that can be used t o detect the end of the internal write cycle. Ready/Busy is available for the M28C17A in PDIP, PLCC and SO packages, and for the M28C16A in TSOP only. OPERATION In order to prevent data corruption and inadvertent write operation s during power-up, a Power On Reset (POR) circuit resets all internal programming cicuitry. Access to t he memory in write mode is allowed after a power-up as specified in Table 7. Read The M28C16A/17A is accessed like a static RAM. When E and G are low with W high, the data addressed is presented on the I/O pins. The I/O pins are high impedance when either G or E is high.
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