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Part: M27C512-80F1X
Category:
Memory
-> EPROM
-> 8 Mb
Description: 512 Kbit 64kb x8 uv EPROM And OTP EPROM
Company: ST Microelectronics, Inc.
Datasheet: Download M27C512-80F1X datasheet File size : 45 kB
Request For quote: Find where to buy M27C512-80F1X
Datasheet text preview:
M27C512
512 Kbit (64Kb x8) UV EPROM and OTP EPROM
5V ± 10% SUPPLY VOLTAGE in READ OPERATION FAST ACCESS TIME: 45ns LOW POWER "CMOS" CONSUMPTION: Active Current 30mA Standby Current 100µA PROGRAMMING VOLTAGE: 12.75V ± 0.25V PROGRAMMING TIMES of AROUND 6sec. (PRESTO IIB ALGORITHM) ELECTRONIC SIGNATURE Manufacturer Code: 20h Device Code: 3Dh
28
28
1
1
FDIP28W (F)
PDIP28 (B)
DESCRIPTION The M27C512 is a 512 Kbit EPROM offered in the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for applications where fast turn-around and pattern experiment at ion are important requirements and is organized as 65,536 by 8 bits. The FDIP28W (window ceramic frit-seal package) has transparent lid which allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure. For applications where the content is programmed only one time and erasure is not required, the M27C512 is offered in PDIP28, PLCC32 and TSOP28 (8 x 13.4 mm) packages.
PLCC32 (C)
TSOP28 (N) 8 x 13.4mm
Figure 1. Logic Diagram
VCC
16 A0-A15
8 Q0-Q7
E
Table 1. Signal Names
A0-A15 Q0-Q7 E GVPP VCC VSS November 1998 Address Inputs Data Outputs Chip Enable Output Enable / Program Supply Supply Voltage Ground
M27C512
GVPP
VSS
AI00761B
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M27C512
Figure 2A. DIP Pin Connections Figure 2B. LCC Pin Connections
AI00762
VSS DU Q3 Q4 Q5
AI00763
A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 VSS
1 2 3 4 5 6 7 M27C512 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC A14 A13 A8 A9 A11 GVPP A10 E Q7 Q6 Q5 Q4 Q3
A7 A12 A15 DU VCC A14 A13
1 32 A6 A5 A4 A3 A2 A1 A0 NC Q0 A8 A9 A11 NC GVPP A10 E Q7 Q6 9 M27C512 25 17
Warning: NC = Not Connected, DU = Don't Use
Figure 2C. TSOP Pin Connections
GVPP A11 A9 A8 A13 A14 VCC A15 A12 A7 A6 A5 A4 A3
22
21
28 1
M27C512
15 14
7
8
AI00764B
A10 E Q7 Q6 Q5 Q4 Q3 VSS Q2 Q1 Q0 A0 A1 A2
DEVICE OPERATION The modes of operations of the M27C512 are listed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for GVPP and 12V on A9 for Electronic Signature. Read Mode The M27C512 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time (tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after a delay of tGLQV from the falling edge of G, assuming that E has been low and the addresses have been stable for at least tAVQV-tGLQV. Standby Mode The M27C512 has a standby mode which reduces t h e active current from 30mA to 100µA The M27C512 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the GVPP input.
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Q1 Q2
M27C512
Table 2. Absolute Maximum Ratings (1)
Symbol TA TBIAS TSTG VIO
(2)
Parameter Ambient Operating Temperature Temperature Under Bias Storage Temperature Input or Output Voltages (except A9) Supply Voltage A9 Voltage Program Supply Voltage
(3)
Value 40 to 125 50 to 125 65 to 150 2 to 7 2 to 7 2 to 13.5 2 to 14
Unit °C °C °C V V V V
VCC VA9
(2)
VPP
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum DC voltage on Input or Output is 0.5V with possible undershoot to 2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns. 3. Depends on range.
Table 3. Operating Modes
Mode Read Output Disable Program Program Inhibit Standby Electronic Signature
Note: X = VIH or VIL, VID = 12V ± 0.5V
E VI L VIL VIL Pulse VIH VIH VIL
GVPP VIL VIH VPP VPP X VIL
A9 X X X X X VID
Q0 - Q7 Data Out Hi-Z Data In Hi-Z Hi-Z Codes
Table 4. Electronic Signature
Identifier Manufacturer's Code Device Code A0 VIL VIH Q7 0 0 Q6 0 0 Q5 1 1 Q4 0 1 Q3 0 1 Q2 0 1 Q1 0 0 Q0 0 1 Hex Data 20h 3Dh
Two Line Output Control Because EPROMs are usually used in larger memory arrays, the product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur.
For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device.
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