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Part: M27C405-100N1TR
Category:
Memory
-> EPROM
-> 8 Mb
Description: 4 Mbit 512kb X 8 OTP EPROM
Company: ST Microelectronics, Inc.
Datasheet: Download M27C405-100N1TR datasheet File size : 45 kB
Request For quote: Find where to buy M27C405-100N1TR
Datasheet text preview:
M27C405
4 Mbit (512Kb x 8) OTP EPROM
5V ± 10% SUPPLY VOLTAGE in READ OPERATION PIN COMPATIBLE with the 4 Mbit, SINGLE VOLTAGE FLASH MEMORY FAST ACCESS TIME: 70ns LOW POWER CONSUMPTION: Active Current 30mA at 5MHz Standb y Current 100µA PROGRAMMING VOLTAGE: 12.75V ± 0.25V PROGRAMMING TIMES Typical 48sec. (PRESTO II Algorithm) Typical 27sec. (On-Board Programming) ELECTRONIC SIGNATURE Manufacturer Code: 20h Device Code: B4
32
1
PDIP32 (B)
PLCC32 (K)
TSOP32 (N) 8 x 20mm
DESCRIPTION The M27C405 is a 4 Mbit EPROM offered in the OTP (one time programmable) range. It is ideally suited for microprocessor systems requiring large programs, in the application where the contents is stable and needs t o be programmed only one time and is organised as 524,288 by 8 bits. The M27C405 is pin compatible with the industry standard 4 Mbit, single voltage Flash memory. It can be considered as a F lash Low Cost solution for production quantitie s. The M27C405 is offered in PDIP32, PLCC32 a nd TSOP32 (8 x 20 mm) packages .
Figure 1. Logic Diagram
VCC
VPP
19 A0-A18
8 Q0-Q7
E
M27C405
Table 1 . Signal Names
A0-A18 Q0-Q7 E G VPP VCC VSS March 1999 Address Inputs Data Outputs Chip Enable Output Enable Program Supply Supply Voltage Ground
G
VSS
AI01601
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M27C405
Figure 2A. DIP Pin Connections Figure 2B. LCC Pin Connections
A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 VSS
1 2 3 4 5 6 7 8 M27C405 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC VPP A17 A14 A13 A8 A9 A11 G A10 E Q7 Q6 Q5 Q4 Q3
A7 A6 A5 A4 A3 A2 A1 A0 Q0
A 12 A 15 A 16 A 18 VCC VPP A 17 1 32 A14 A13 A8 A9 A11 G A10 E Q7 9 M27C405 25 17 Q1 Q2 VSS Q3 Q4 Q5 Q6
AI01603
AI01602
Figure 2C. TSOP Pin Connections
A11 A9 A8 A13 A14 A17 VPP VCC A18 A16 A15 A12 A7 A6 A5 A4
1
32
8 9
M27C405 (Normal)
25 24
16
17
AI01604
G A10 E Q7 Q6 Q5 Q4 Q3 VSS Q2 Q1 Q0 A0 A1 A2 A3
DEVICE OPERATION The modes of operationsof t he M27C405 are listed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for Vpp and 12V on A9 for Electronic Signature. Read Mode The M27C405 has two control functions, both of which must be logically active in order to obtain data at the output s. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to t he output pins, independen t of device selection. Assuming that the addresses are stable, the address access time (tAVQV) is equal to the delay from E t o output (tELQV). Data is available at the output after a delay of tGLQV from the f alling edge of G, assuming that E has been low and the addresses have been stable for at least t AVQV-tGLQV. Standby Mode The M27C405 ha s a standby mode which reduces the a c tiv e c urren t f rom 30 mA t o 10 0µA . T he M27C405 is placed in the standby mode by applying a CMOS high signal t o the E input. When in the standby mode, the outputs are in a high impedance state, independe nt of t he G input.
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M27C405
Table 2. Absolute Maximum Ratings ( 1)
Symbol TA TBIAS TSTG VIO ( 2) V CC VA9
(2)
Parameter Am bient Operating Temperature Temperature Under Bias Storage Temperature Input or Output Voltages (except A9) Supply Voltage A9 Voltage Program Supply Voltage
(3)
Value 40 to 125 50 to 125 65 to 150 2 to 7 2 to 7 2 to 13.5 2 to 14
U nit °C °C °C V V V V
VPP
N otes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum R atings" may c ause permanent damage t o the device. These are stress ratings only and operation of the device at these or any other conditions above those indic ated i n the Operating sections of this s pecification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum DC v oltage on Input or Output is 0.5V with possible undershoot to 2.0V for a peri od less t han 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less t han 20ns. 3. Depends on range.
Table 3 . Operating Modes
Mode Read Output Disable Program Verify Program Inhibit Standby Electronic Signature
Note: X = VIH or VIL, VI D = 12V ± 0.5V
E VI L VI L VIL Pulse VIH VIH VIH VI L
G VI L VIH VIH VI L VIH X VI L
A9 X X X X X X VID
VPP VCC or VSS VCC or VSS VPP VPP VPP VCC or VSS VCC
Q0 - Q7 D ata Out H i-Z D ata In D ata Out H i-Z H i-Z C odes
Table 4 . Electronic Signature
Identifier Manufacturer's Code Device Code A0 V IL VIH Q7 0 1 Q6 0 0 Q5 1 1 Q4 0 1 Q3 0 0 Q2 0 1 Q1 0 0 Q0 0 0 Hex D ata 20h B4h
Two Line Output Control Because OTP EPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multi ple memory co nnection. The t wo line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contentio n will not occur.
For the most efficient use of these two control lines, E should be decoded and used as t he primary device selecting f unction, while G should be made a common connection t o all devices in the array and connected to the READ line from the system control bus. T his ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device.
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