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Part: M25P20
Category:
Memory
-> Flash
-> Serial Flash
-> Serial Flash for Code Storage
Description: 2 Mbit, Low Voltage, Serial Flash Memory With 25 MHZ Spi Bus Interface
Company: ST Microelectronics, Inc.
Datasheet: Download M25P20 datasheet File size : 331 kB
Request For quote: Find where to buy M25P20
Datasheet text preview:
M25P20
2 Mbit, Low Voltage, Serial Flash Memory With 25 MHz SPI Bus Interface
FEATUR ES SUMMARY s 2 Mbit of Flash Memory
s
Figure 1. Packages
Page Program (up to 256 Bytes) in 1.5ms (typical) Sector Erase (512 Kbit) in 2 s (typical) Bulk Erase (2 Mbit) in 3 s (typical) 2.7 V to 3.6 V Single Supply Voltage SPI Bus Compatible Serial Interface 25 MHz Clock Rate (maximum) Deep Power-down Mode 1 ľA (typical) Electronic Signature (11h) More than 100,000 Erase/Program Cycles per Sector More than 20 Year Data Retention
s s s s s s s s
8 1
SO8 (MN) 150 mil width
s
VFQFPN8 (MP) (MLP8)
December 2002
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M25P20
SUMMARY DESCRIPTION The M25P20 is a 2 Mbit (256K x 8) Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus . The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 4 sectors, each containing 256 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 1024 pages, or 262,144 bytes. The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction. Figure 2. Logic Diagram
VCC
Figure 3. SO and VFQFPN Connections
M25P20 S Q W VSS 1 2 3 4 8 7 6 5
AI04081B
VCC HOLD C D
D C S W HOLD M25P20
Q
Note: 1. See page 30 (onwards) for package dimensions, and how to identify pin-1.
VSS
AI04080
Table 1. Signal Names
C D Q Serial Clock Serial Data Input Serial Data Output Chip Select Write Protect Hold Supply Voltage Ground
S
W HOLD VCC VSS
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M 25P20
SIGNA L DESCRIPTION Serial Data Output (Q). This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). Serial Data Input (D). This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C). Serial Clock (C). This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C). Chip Select (S). When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress, the device will be in the Standby mode
(this is not the Deep Power-down mode). Driving Chip Select (S) Low enables the device, placing it in the active power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction. Hold (HOLD). The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. Write Protect (W). The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP1 and BP0 bits of the Status Register).
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