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Part: M25P10-V
Category:
Memory
-> Flash
-> Serial Flash
-> Serial Flash for Code Storage
Description: Not For Design - 1 Mbit, Low Voltage, Serial Flash Memory With 20 MHZ Spi Bus Interface
Company: ST Microelectronics, Inc.
Datasheet: Download M25P10-V datasheet File size : 13 kB
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Datasheet text preview:
M25P10
1 Mbit, Low Voltage, Serial Flash Memory With 20 MHz SPI Bus Interface
NOT FOR NEW DESIGN
FEATUR ES SUMMARY This device is now designated as "Not for New Design". Please use the M25P10-A in all future designs (as described in application note AN1511). s 1 Mbit of Flash Memory
s
Figure 1. Packages
Page Program (up to 128 Bytes) in 3 ms (typical) Sector Erase (256 Kbit) in 1 s (typical) Bulk Erase (1 Mbit) in 2 s (typical) 2.7 V to 3.6 V Single Supply Voltage SPI Bus Compatible Serial Interface 20 MHz Clock Rate (maximum) Deep Power-down Mode 1 ľA (typical) Electronic Signature More than 100,000 Erase/Program Cycles per Sector More than 20 Year Data Retention
s s s s s s s s
8 1
SO8 (MN) 150 mil width
s
February 2002
This is information on a product still in production but not recommended for new designs.
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M25P10
SUMMARY DESCRIPTION The M25P10 is a 1 Mbit (128K x 8) Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus . The memory can be programmed 1 to 128 bytes at a time, using the Page Program instruction. The memory is organized as 4 sectors, each containing 256 pages. Each page is 128 bytes wide. Thus, the whole memory can be viewed as consisting of 1024 pages, or 131,072 bytes. The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction. Figure 2. Logic Diagram
VCC
Figure 3. SO Connections
M25P10 S Q W VSS 1 2 3 4 8 7 6 5
AI03745
VCC HOLD C D
D C S W HOLD M25P10
Q
VSS
AI03744
Table 1. Signal Names
C D Q Serial Clock Serial Data Input Serial Data Output Chip Select Write Protect Hold Supply Voltage Ground
S
W HOLD VCC VSS
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M 25P10
SIGNA L DESCRIPTION Serial Data Output (Q). This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). Serial Data Input (D). This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C). Serial Clock (C). This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C). Chip Select (S). When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress, the device will be in the Standby mode
(this is not the Deep Power-down mode). Driving Chip Select (S) Low enables the device, placing it in the active power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction. Hold (HOLD). The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. Write Protect (W). The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP1 and BP0 bits of the Status Register).
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