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Part: D950-CORE
Category:
DSPs (Digital Signal Processors)
-> DSP Block
Description: 16-bit Fixed Point Digital Signal Processor DSP Core
Company: ST Microelectronics, Inc.
Datasheet: Download D950-CORE datasheet File size : 62 kB
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Datasheet text preview:
D9 50-CORE
16-Bit Fixed Point Digital Signal Processor (DSP) Core
PRELIMINARY DATA
s
UNI T
YD-bus XD-bus
s
ADDRESS CALCULATION UNIT
16 XA-bus YA-bus 16 16 16
s
PROG RAM CO NTROL UNIT
3 ID-bus IA-bus 16 16
s
11 CONTROL
8
14 TEST & EMULATION
PO/P7
s
s
s
s
s
s
Peripherals and Memory s M acrocells for peripherals such as the bus switch unit, interrupt controller and DMA controller s S t andard cells library, I/O library s M em ory generators for RAM and ROM Development Tools s JT AG PC board with graphic windowed high level source debugger for AS-DSP emulation s Co mpl ete crash-barrier chain (assembler / simulator / linker) running on PC and SUN, s Co mpl ete GNU chain (assembler / simulator / linker / C compiler / C debugger) for SUN s V HDL model (SYNOPSYS & MENTOR)
4 September 1997
This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice
VDD VSS
PROGRAM MEMORY
DATA MEMORY
6
OUTPUT CLO CKS
s
Perform ance s 66 Mips - 15ns instruction cycle time Memory Organization s HA RVA RD architecture s Two 64k x 16-bit data memory spaces s One 64k x 16-bit program memory space s 2 stacks in data memory spaces Fast and Flexible Buses s Two 16-bit address 16-bit data nonmultiplexed data buses s One 16-bit address 16-bit data nonmultiplexed instruction bus Data Calculation Unit s 16 x 16-bit parallel multiplier s 40-bit barrel shifter unit s 40-bit ALU s Two 40-bit extended precision accumulators s Fract ional and integer arithmetic with support for floating point and multi-precision s 16-bit bit manipulation unit (BMU) Address Calculation Unit s Two address calculation units with modulo and bit-reverse capability s 2 x 16-bit address registers s 4 x 16-bit index registers s2 x 16-bit base and maximum address registers for modulo addressing Program Control Unit s 16-bit program counter s 3 Hardware Loop Capabilities Power Consumption s Si ngle 3.3V power supply s Low-power standby mode Electrical Characteristics s Operat ing frequency down to DC Channels s Gene ra l purpose 8-bit I/O port s Dedicated hardware for Emulation and Test, IEEE 1149.1 (JTAG) interface compatible
DATA CALCULATIO N
CLKIN
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Table of Contents
1 2 3 4 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 FUNCTIONAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 BLOCK DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 DATA CALCULATION UNIT (DCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 4.2.1 4.2.2 4.2.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 4.4.1 4.4.2 4.5.1 4 .5 .2 5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Barrel Shifter Unit (BSU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Arithmetic and Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Bit Manipulation Unit (BMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Instruction pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Loop Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Sequence control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Halting program execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Memory Moves with Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 STA: Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 CCR: Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2 ADDRESS CALCULATION UNIT (ACU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3 PROGRAM CONTROL UNIT (PCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.4 GENERAL PURPOSE P-PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.5 COMMON CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SOFTWARE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.2 REGISTER LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.3 CONDITION LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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5.4 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 6 Assignment Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 ALU Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Conditional Assignment Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Loop Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Co-processor Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Stack Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.5 INSTRUCTION CYCLE AND WORD COUNT . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.1 DC ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.2 DC ELECTRICAL CHARACTERISTICS (CORE LEVEL) . . . . . . . . . . . . . . . . . . 56 6.3 AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 7 Bus AC Electrical Characterstics (for X, Y and I buses) . . . . . . . . . . . . . . 57 Control I/O Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Wa it States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 HOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 JUMP on Port Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
ANNEX - HARDWARE PERIPHERAL LIBRARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7.1 CO-PROCE SSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7.2 BUS SWITCH UNIT (BSU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.2.1 7.2.2 7.2.3 7.2.4 7.3.1 7.3.2 7.3.3 7.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 I/O interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 B SU control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 I/O interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Interrupt Controller Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . 73 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
7.3 INTERRUP T CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.4 DMA CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
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7.4.2 7.4.3 7.4.4 7.5.1 7.5.2 8 I/O interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 DMA Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.5 EMULATION AND TEST UNIT (EMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
APPENDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.1 MEMORY MAPPING (Y-MEMORY SPACE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 General mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Registers Related to the D950-CORE . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Registers related to the interrupt controller . . . . . . . . . . . . . . . . . . . . . . . 87 Registers related to the DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . 88 Registers related to the Bus Switch Unit . . . . . . . . . . . . . . . . . . . . . . . . 88
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D950-Core
1
Introduction
The D950-Core is a general purpose programmable 16-bit fixed point Digital Signal Processor Core , designed for multimedia, telecom and datacom applications. The D950-Core is a core product, used in combination with standard or custom peripherals from the standard cell libra ry. The peripherals are implemented around the core on the same silicon die, for application specific DSP silicon chip design. The main blocks of the D950-Core include an arithmetic data calculation unit, a program co ntrol unit and an address calculation unit, able to manage up to 64k (program) and 128k (data) x 16-bit memory spaces. Standard peripherals from the macrocell library include an Emulation Unit, a Bus Switch Unit, an Interrupt Controller, a DMA Controller, a Timer and a Synchronous Serial Port. Memory can be added for programs or data and dedicated memory ce lls can be generated by use of RAM and ROM memory generators. The development of application specific peripherals is simplified by using the standard cells library. A set of high level hardware and software development tools and a complete design package, give the user a substantial advantages in the form of a performant design environment, rapid prototyping, first time silicon success and built-in test strategies for a global solution in AS-DSP development: Figure 1.1 shows an architecture example for an AS-DSP used for audio decoding (Dolby AC3, MPEG). Figure 1.1 AS-DSP Architecture Example
PERIPHERAL B PERIPHERAL A CHANNEL 1 CHANNEL 2 CHANNEL 3 PERIPHERAL C PERIPHERAL D
CHANNEL 0
DMA CONTROLLER
ON-CHIP MEMORY I N T E R R U P T C O N T R O L L E R DATA X-BUS ON-CHIP MEMORY MEMORY BUS SWITCH UNIT PROGRAM I-BUS MEMORY TAP
D950-CORE
Y-BUS ON-CHIP MEMORY
EMU
AS-DSP
VR02015
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Others parts begin by d9
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