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Part: S3FK215
Category:
Microcontrollers
-> CalmRISC Core->S3CK Series
Description: Description = S3FK215 8-Bit CMOS Microcontroller ;; ROM(KB) = 16 ;; RAM(bytes) = 1K ;; I/o Pins = 39 ;; Interrupt (Int/Ext) = 9/4 ;; Timer/counters = BT/WT/8TCx2/16TCx2 ;; Serial Interface = Sio ;; LCD (Seg/Com) = 30/4 ;; ADC (BitxCh) = 10x8 ;; PWM(BitxCh) = 8x2,16x1 ;; Max. OSC.Freq. (MHz) = 8 ;; VDD(V) = 2.0~5.5 ;; Other Features = 8x8 Multiplication ;; Package = 80QFP ;; Production Status = Mass Production
Company: Samsung Semiconductor, Inc.
Datasheet: Download S3FK215 datasheet File size : 40 kB
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Datasheet text preview:
S3CB519/FB519
PRODUCT OVERVIEW
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OVERVIEW
PRODUCT OVERVIEW
The S3CB519/FB519 single-chip CMOS microcontroller is designed for high performance using Samsung's new 8-bit CPU core, CalmRISC. CalmRISC is an 8-bit low power RISC microcontroller. Its basic architecture follows Harvard style, that is, it has separate program memory and data memory. Both instruction and data can be fetched simultaneously without causing a stall, using separate paths for memory access. Represented below is the top block diagram of the CalmRISC microcontroller.
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PRODUCT OVERVIEW
S3CB519/FB519
20 PA[19:0] PD[15:0] Program Memory Address Generation Unit PC[19:0] 20 8 8 HS[0] Hardware Stack TBH DO[7:0] ABUS[7:0] BBUS[7:0] DI[7:0] ALUL ALUR R0 R1 R2 ALU Flag R3 GPR TBL HS[15]
RBUS
SR1 ILX Data Memory Address Generation Unit ILH
SR0 ILL IDL0
DA[15:0]
IDH IDL1 SPR
Figure 1-1. Top Block Diagram
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S3CB519/FB519
PRODUCT OVERVIEW
The CalmRISC building blocks consist of: -- An 8-bit ALU -- 16 general purpose registers (GPR) -- 11 special purpose registers (SPR) -- 16-level hardware stack -- Program memory address generation unit -- Data memory address generation unit Sixteen GPRs are grouped into four banks (Bank0 to Bank3), and each bank has four 8-bit registers (R0, R1, R2, and R3). SPRs, designed for special purposes, include status registers, link registers for branch-link instructions, and data memory index registers. The data memory address generation unit provides the data memory address (denoted as DA[15:0] in the top block diagram) for a data memory access instruction. Data memory contents are accessed through DI[7:0] for read operations and DO[7:0] for write operations. The program memory address generation unit contains a program counter, PC[19:0], and supplies the program memory address through PA[19:0] and fetches the corresponding instruction through PD[15:0] as the result of the program memory access. CalmRISC has a 16-level hardware stack for low power stack operations as well as a temporary storage area.
Instruction Fetch (IF)
Instruction Decode/ Data Memory Access (ID/MEM)
Execution/Writeback (EXE/WB)
Figure 1-2. CalmRISC Pipeline Diagram CalmRISC has a 3-stage pipeline as described below: As can be seen in the pipeline scheme, CalmRISC adopts a register-memory instruction set. In other words, data memory where R is a GPR can be one operand of an ALU instruction as shown below: The first stage (or cycle) is the Instruction fetch stage (IF for short), where the instruction pointed by the program counter, PC[19:0] , is read into the Instruction Register (IR for short). The second stage is the Instruction Decode and Data Memory Access stage (ID/MEM for short), where the fetched instruction (stored in IR) is decoded and data memory access is performed, if necessary. The final stage is the Execute and Write-back stage (EXE/WB), where the required ALU operation is executed and the result is written back into the destination registers. Since CalmRISC instructions are pipelined, the next instruction fetch is not postponed until the current instruction is completely finished but is performed immediately after completing the current instruction fetch. The pipeline stream of instructions is illustrated in the following diagram.
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Others parts begin by s3
S3-1 S3-2 S3-3 S3-4
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