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Part: M368L6423CT1
Category:
Memory
-> DRAM
-> DDR SDRAM
-> Modules
-> Unbuffered DIMM
Description: Description = M368L6423CT1 64Mx64 DDR Sdram 184pin Dimm Based on 32Mx8 ;; Density(MB) = 512 ;; Organization = 64Mx64 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = B3,A2,B0,A0 ;; #of Pin = 184 ;; Power = C,l ;; Component Composition = (32Mx8)x16 ;; Production Status = Eol ;; Comments = Replaced BY M368L6423CTL
Company: Samsung Semiconductor, Inc.
Datasheet: Download M368L6423CT1 datasheet File size : 224 kB
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Datasheet text preview:
M368L6423CT1
184pin Unbuffered DDR SDRAM MODULE
512MB DDR SDRAM MODULE
(64Mx64(32Mx64*2 bank) based on 32Mx8 DDR SDRAM)
Unbuffered 184pin DIMM 64-bit Non-ECC/Parity
Revision 0.0 September. 2001
Rev. 0.0 Sep. 2001
M368L6423CT1
Revision History
Revision 0 (Sep 2001)
1 . First release for internal usage
184pin Unbuffered DDR SDRAM MODULE
Rev. 0.0 Sep. 2001
M368L6423CT1
184pin Unbuffered DDR SDRAM MODULE
M 3 6 8 L 6 4 2 3 C T 1 DDR SDRAM 184pin DIMM
64Mx64 DDR SDRAM 184pin DIMM based on 32Mx8 GENERAL DESCRIPTION
The Samsung M368L6423CT1 is 32M bit x 64 Double Data R a t e SDRAM high density memory module based on4th gen. o f 256Mb DDR SDRAM respectively. The Samsung M368L6423CT1 consists of sixteen CMOS 32M x 8 bit with 4banks Double Data Rate SDRAMs in 66pin T S O P - I I ( 4 0 0 m i l ) packages mounted on a 184pin glass-epoxy s u b s t r a t e . Four 0.1uF decoupling capacitors are mounted on t h e printed circuit board in parallel for each DDR SDRAM. The M 3 6 8 L 6 4 2 3 C T 1 Dual In-line Memory Module and is intended f o r mounting into 184pin edge connector sockets. Synchronous design allows precise cycle control with the use o f system clock. I/O transactions are possible on every clock c y c l e . Range of operating frequencies, programmable latenc i e s and burst lengths allows the same device to be useful for a v a r i e t y of high bandwidth, high performance memory system applications.
FEATURE
· Performance range P a r t No. M a x Freq. Interface M368L6423CT1-C(L)B3 167MHz(6.0ns@CL=2.5) M368L6423CT1-C(L)A2 133MHz(7.5ns@CL=2) M368L6423CT1-C(L)B0 133MHz(7.5ns@CL=2.5) M368L6423CT1-C(L)A0 100MHz(10ns@CL=2) · Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V SSTL_2
· Double-data-rate architecture; two data transfers per clock cycle
· Bidirectional data strobe(DQS) · Differential clock inputs(CK and CK) · DLL aligns DQ and DQS transition with CK transition · Programmable Read latency 2, 2.5 (clock) · Programmable Burst length (2, 4, 8) · Programmable Burst type (sequential & interleave) · Edge aligned data output, center aligned data input · Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) · Serial presence detect with EEPROM · PCB : Height 1250 (mil), double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin F r o n t Pin F r o n t P i n
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CK1 /CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 *CB0 *CB1 VDD *DQS8 A0 *CB2 VSS *CB3 BA1 KEY DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92
PIN DESCRIPTION
Pin Back P i n Name
A 0 ~ A12 B A 0 ~ BA1 D Q 0 ~ DQ63 D Q S 0 ~ DQS7 CKE0,CKE1 C S 0, CS1 RAS CAS WE DM0 ~ 7 VDD VDDQ VSS VREF VDDSPD SDA SCL SA0 ~ 2 VDDID
F r o n t Pin
VDDQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD */CS2 DQ48 DQ49 VSS /CK2 CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123
Back
VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC *A13 VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 CKE1 VDDQ *BA2 DQ20 A12 VSS DQ21 A11 DM2 VDD DQ22 A8 DQ23
Pin
124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153
Back
VSS A6 DQ28 DQ29 VDDQ DM3 A3 DQ30 VSS DQ31 *CB4 *CB5 VDDQ CK0 /CK0 VSS *DM8 A10 *CB6 VDDQ *CB7 KEY VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44
Function
Address input (Multiplexed) Bank Select Address D a t a input/output D a t a Strobe input/output Clock enable input Chip select input Row address strobe Column address strobe W r i t e enable Data - in mask P o w e r supply (2.5V) P o w e r Supply for DQS(2.5V) Ground P o w e r supply for reference S e r i a l EEPROM Power Supply (2.3V to 3.6V) Serial data I/O Serial clock A d d r e s s in EEPROM VDD identification flag
154 /RAS 155 DQ45 156 V D D Q 157 /CS0 158 /CS1 159 DM5 160 VSS 161 DQ46 162 DQ47 163 */CS3 164 V D D Q 165 DQ52 166 DQ53 167 NC 168 VDD 169 DM6 170 DQ54 171 DQ55 172 V D D Q 173 NC 174 DQ60 175 DQ61 176 VSS 177 DM7 178 DQ62 179 DQ63 180 V D D Q 181 SA0 182 SA1 183 SA2 184 VDDSPD
CK0, CK0 ~ CK2, CK2 Clock input
NC No connection * These pins are not used in this module.
S A M S U N G ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.0 Sep. 2001
Others parts begin by m3
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