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Part: PCI9060SD
Category:
Interface and Interconnect
-> PCI
-> I/O Accelerator
Description: The Pci 9060 Family Was The First Full Featured Pci Interface Chip on The Market And Was Recognized as The Industry Standard For Pci Interface Devices.
Company: PLX Technology, Inc.
Datasheet: Download PCI9060SD datasheet File size : 3358 kB
Request For quote: Find where to buy PCI9060SD
Datasheet text preview:
PCI 9060SD Data Sheet
Version 1.0 April 17, 1997
Website: http://www.plxtech.com Email: apps@plxtech.com Phone: 408-774-9060 FAX: 408-774-2169
PCI 9060SD
TABLE OF CONTENTS
TABLE OF CONTENTS
1. GENERAL DESCRIPTION ........1 1.1 MAJOR FEATURES.............1 1.2 COMPARISON OF PCI 9060 AND PCI 9060SD ..2 2. BUS OPERATION ......3 2.1 PCI BUS CYCLES.......3
2.1.1 PCI Target Command Codes ..........3 2.1.2 PCI Master Command Codes..........3
2.1.2.1 DMA Master Command Codes.......... 3
2.2 LOCAL BUS CYCLES ..........3
2.2.1 Local Bus Slave .............3 2.2.2 Local Bus Master ...........3
2.2.2.1 Ready/Wait State Control......... 3 2.2.2.2 Burst Mode and Continuous Burst Mode (BTERM "Burst Terminate" Mode) .... ........ 4 2.2.2.3 Recovery States ........ 4 2.2.2.4 Local Bus Read Accesses........ 4 2.2.2.5 Local Bus Write Accesses........ 5 2.2.2.6 Direct Slave Write Access to 8- and 16-bit bus......... 5 2.2.2.7 Local Bus Data Parity...... 5 2.2.2.8 Local Bus Little/Big Endian....... 5
3. FUNCTIONAL DESCRIPTION ............ .....7 3.1 RESET .........7
3.1.1 PCI Bus Input RST# ......7 3.1.2 Local Bus Input LRESETi# .....7 3.1.3 Local Bus Output LRESETo# ..........7 3.1.4 Software Reset ..............7
3.2 PCI 9060SD INITIALIZATION ........ .....7 3.3 EEPROM ......7
3.3.1 Short EEPROM Load.....7 3.3.2 Long EEPROM Load .....8 3.3.3 Extra Long EEPROM Load...10 3.3.4 Internal Register Access.......10 3.3.5 PCI Bus Access to Internal Registers...........11 3.3.6 Local Bus Access to Internal Registers .. ......11
3.4 DIRECT DATA TRANSFER MODES.........12
©PLX Technology, Inc., 1997
Page iii
Version 1.0
PCI 9060SD
TABLE OF CONTENTS
3.4.1 Direct Bus Master Operation ......12 3.4.2 Direct Slave Operation (PCI Master to Local Bus Access)...12
3.4.2.1 PCI to Local Address Mapping ........ 13 3.4.2.1.1 Local Bus Initialization Software.............. 13 3.4.2.1.2 PCI Initialization Software......... 13 3.4.2.2 Direct Slave Lock .... 15
3.4.3 Direct Slave Priority .....15
3.5 DMA OPERATION .............15
3.5.1 Non-Chaining Mode DMA .....16 3.5.2 Chaining Mode DMA....17 3.5.3 DMA Data Transfers ....18
3.5.3.1 Local to PCI Bus DMA Transfer ...... 18 3.5.3.2 PCI to Local Bus DMA Transfer ...... 19
3.5.4 Unaligned Transfers ....19 3.5.5 Demand Mode DMA ....19 3.5.6 DMA Priority........19 3.5.7 DMA Arbitration............20
3.5.7.1 End Of Transfer (EOT1#) Input ....... 20 3.5.7.2 Local Latency and Pause Timers ........ ........... 20
3.6 BREQ INPUT ......20 3.7 DOORBELL REGISTERS ...........20 3.8 MAILBOX REGISTERS......20 3.9 INTERRUPTS ........ ............20
3.9.1 PCI Interrupts (INTA#) ..........20
3.9.1.1 Local to PCI Doorbell Interrupt ........ 20 3.9.1.2 Local Interrupt Input ...... 21 3.9.1.3 Master/Target Abort Interrupt .......... 21
3.9.2 Local Interrupts (LINTo#)......21
3.9.2.1 PCI to Local Doorbell Interrupt ........ 21 3.9.2.2 Built-In Self Test Interrupt (BIST) .... 21 3.9.2.3 DMA Channel 1 Interrupt........ 21
3.9.3 PCI SERR# (PCI NMI)..........22 3.9.4 Local LSERR# (Local NMI)...22
4. REGISTERS ....23 4.1 REGISTER ADDRESS MAPPING .............23 4.2 PCI CONFIGURATION REGISTERS ........25
4.2.1 PCI Configuration ID Register (Offset 00h) ..25
©PLX Technology, Inc., 1997
Page iv
Version 1.0
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