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Part: PCI9060ES
Category:
Interface and Interconnect
-> PCI
-> I/O Accelerator
Description: The Pci 9060 Family Was The First Full Featured Pci Interface Chip on The Market And Was Recognized as The Industry Standard For Pci Interface Devices.
Company: PLX Technology, Inc.
Datasheet: Download PCI9060ES datasheet File size : 3358 kB
Request For quote: Find where to buy PCI9060ES
Datasheet text preview:
PCI 9060ES
November 1995 PCI Bus Master Interface Chip for VERSION 1.0 Adapters and Embedded Systems ________________________________________________________________________________
Features _________________________
General Description _______________
The PCI9060ES provides a compact high performance PCI bus master interface for adapter boards and embedded systems. The chip's local bus may connect directly to Intel's 80960 processor chips or to any other similar local buses. The PCI9060ES allows the i960® processors and other intelligent controllers to perform direct bus master transfers on the PCI bus. The PCI9060ES also enables the local processor to configure other PCI devices in the system, an important feature for embedded systems. The PCI9060ES supports both memory mapped and I/O mapped accesses to the local bus from the PCI bus.
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PCI Bus Master and Bus Slave transfers up to 132 megabytes/sec supporting three architectures: - PCI Direct Master adapter - PCI Slave adapter - PCI embedded system Two bi-directional FIFOs (each 16 Lwords deep) for zero wait-state burst operation; one for Direct Master interface and one for Direct Slave interface Supports both multiplexed and non-multiplexed local buses, 32 or 16 bit. Connects directly to Intel i960®Cx, Hx, Jx, Kx and Sx processors Supports PCI bus accesses as both a PCI bus Master and Target
Two independent bi-directional FIFOs support zero wait· Local bus can run asynchronously to the PCI clock. state Direct Slave burst transfers between host and local · Four 32 bit mailbox and two 8 bit doorbell registers memory and Direct Bus Master transfers between a Local Bus Master and the PCI bus. · Supports Little Endian/Big Endian swapping · _____power _____in______Plastic_QFP __________________________________________________ Low CMOS 208 Pin Package _ ____ _ ____ ___
Figure 1. Typical PCI 9060ES applications ________________________________________________________________________________
© PLX Technology, Inc., 1995 PLX Technology, Inc., 390 Potrero Avenue, Sunnyvale, CA 94086 (408) 774-9060 FAX (408) 774-2169 Products and Company names are trademarks/registered trademarks of their respective holders
TABLE OF CONTENTS ________________________________________________________________________________
TABLE OF CONTENTS
1. SECTION 1 - PCI 9060ES GENERAL DESCRIPTION ...... 5 2. SECTION 2 - BUS OPERATION ...... 7 2.1 PCI BUS CYCLES............ 7 2.1.1 PCI Target Command Codes ............. 7 2.1.2 PCI Master Command Codes............. 7
2.1.2.1 Direct Local to PCI Command Codes............ 7
2.2 LOCAL BUS CYCLES ...... 8 2.2.1 Local Bus Slave......... 8 2.2.2 Local Bus Master ....... 8
2.2.2.1 Ready/Wait State Control ..... 8 2.2.2.2 Burst Mode and Continuous Burst Mode (BTERM "Burst Terminate" mode) ........... 8 2.2.2.3 Recovery States ... 8 2.2.2.4 Local Bus Read Accesses..... 9 2.2.2.5 Local Bus Write Accesses..... 9 2.2.2.6 Direct Slave Write Access to 8 and 16 bit bus ........ 9 2.2.2.7 Local Bus Data Parity ........... 9 2.2.2.8 Local Bus Little/Big Endian .......... 10
3. SECTION 3 - FUNCTIONAL DESCRIPTION.... 11 3.1 PCI 9060ES INITIALIZATION....... 11 3.2 RESET............ 11 3.2.1 PCI Bus Input RST#.......... 11 3.2.2 Local Bus Input LRESETi#...... 11 3.2.3 Local Bus Output LRESETo#........... 11 3.2.4 Software Reset ........ 11 3.3 EEPROM ........ 11 3.3.1 LONG EEPROM LOAD .... 12 3.3.2 SHORT EEPROM LOAD .. 13 3.4 INTERNAL REGISTER ACCESS...... 13 3.4.1 PCI Bus Access to Internal Registers ........ 14 3.4.2 Local Bus Access to Internal Registers...... 14 3.5 DIRECT DATA TRANSFER MODES ...... 15 3.5.1 Direct Bus Master Operation (Local Master to PCI Bus Access) ....... ......... 15 3.5.2 Direct Slave Operation (PCI Master to Local Bus Access)......... 18
3.5.2.1 PCI to Local Address Mapping..... 18 3.5.2.2 Deadlock and BREQo ......... 20 3.5.2.3 Direct Slave Lock....... 21
3.5.3 Arbitration ....... 21
3.5.3.1 Local Latency and Pause Timers. ...... 21
3.6 BREQ INPUT. ... 21 3.7 DOORBELL REGISTERS...... 22 3.8 MAILBOX REGISTERS ........ 22 3.9 INTERRUPTS ..... 22 3.9.1 PCI Interrupts (INTA#) ...... 22
3.9.1.1 Doorbell Interrupt....... 22 3.9.1.2 Local Interrupt Input............ 22 3.9.1.3 Master/Target Abort Interrupt ....... 23
3.9.2 Local Interrupts (LINTo#) .. 23
3.9.2.1 Doorbell Interrupt....... 23 3.9.2.2 Built In Self Test Interrupt (BIST) .......... 23
3.9.3 PCI SERR# (PCI NMI) ..... 23 3.9.4 Local LSERR# (Local NMI) ............ 24
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Section C
PCI9060ES
TABLE OF CONTENTS ________________________________________________________________________________
4. SECTION 4 - REGISTERS ...... 25 4.1 REGISTER ADDRESS MAPPING .... 25 4.2 PCI CONFIGURATION REGISTERS...... 27 4.2.1 PCI Configuration ID Register (Offset 00h) ........ 27 4.2.2 PCI Command Register (Offset 04h)......... 27 4.2.3 PCI Status Register (Offset 06h)...... 28 4.2.4 PCI Revision ID Register (Offset 08h)....... 28 4.2.5 PCI Class Code Register (Offset 09 - 0Bh) ........ 29 4.2.6 PCI Cache Line Size Register (Offset 0Ch)........ 29 4.2.7 PCI Latency Timer Register (Offset 0Dh).. 29 4.2.8 PCI Header Type Register (Offset 0Eh) .... 29 4.2.9 PCI Built-In Self Test (BIST) Register (PCI Offset 0Fh)..... 30 4.2.10 PCI Base Address Register for Memory Access to Runtime Registers (Offset 10h)......... 30 4.2.11 PCI Base Address Register for I/O Access to Runtime Registers(Offset 14h)......... 31 4.2.12 PCI Base Address Register for Memory Access to Local Address Space 0 (Offset 18h).. 31 4.2.13 PCI Base Address Register (Offset 1Ch).......... 31 4.2.14 PCI Base Address Register (Offset 20h) .......... 31 4.2.15 PCI Base Address Register (Offset 24h) .......... 32 4.2.16 PCI Base Address Register (Offset 28h) .......... 32 4.2.17 PCI Base Address Register (Offset 2Ch).......... 32 4.2.18 PCI Expansion ROM Base Register (Offset 30h).... 32 4.2.19 PCI Interrupt Line Register (Offset 3Ch).. 32 4.2.20 PCI Interrupt Pin Register (Offset 3Dh) ... 33 4.2.21 PCI Min_Gnt Register (Offset 3Eh) ......... 33 4.2.22 PCI Max_Lat Register (Offset 3Fh) ......... 33 4.3 LOCAL CONFIGURATION REGISTERS ........... 34 4.3.1 Local Address Space 0 Range Register for PCI to Local Bus (PCI 00h) (LOC 80h) ........... 34 4.3.2 Local Address Space 0 Local Base Address (Re-map) Register for PCI to Local Bus (PCI 04h) (LOC 84h)........ 34 4.3.3 Local Arbitration Register (PCI 08h) (LOC 88h)........ 35 4.3.4 Big/Little Endian Descriptor Register (PCI 0ch) (LOC 8ch) ......... 35 4.3.5 Local Expansion ROM Range Register for PCI to Local Bus (PCI 10h) (LOC 90h)............ 36 4.3.6 Local Expansion ROM Local Base Address (Re-map) register for PCI to Local Bus and BREQo Control (PCI 14h) (LOC 94h)........ 36 4.3.7 Local Bus Region Descriptor for PCI to Local Accesses Register (PCI 18h) (LOC 98h) ..... 37 4.3.8 Local Range register for Direct Master to PCI (PCI 1Ch) (LOC 9Ch) ......... 38 4.3.9 Local Bus Base Address register for Direct Master to PCI Memory (PCI 20h) (LOC A0h).......... 38 4.3.10 Local Base Address for Direct Master to PCI IO/CFG Register (PCI 24h) (LOC A4h) ...... 38 4.3.11 PCI Base Address (Re-map) register for Direct Master to PCI (PCI 28h) (LOC A8h) ...... 39 4.3.12 PCI Configuration Address Register for Direct Master to PCI IO/CFG (PCI 2Ch) (LOC ACh) ... 39 4.4 SHARED RUNTIME REGISTERS .... 40 4.4.1 Mailbox Register 0 (PCI 40h) (LOC C0h) .. 40 4.4.2 Mailbox Register 1 (PCI 44h) (LOC C4h) .. 40 4.4.3 Mailbox Register 2 (PCI 48h) (LOC C8h) .. 40 4.4.4 Mailbox Register 3 (PCI 4Ch) (LOC CCh) .......... 40 4.4.5 PCI to Local Doorbell Register (PCI 60h) (LOC E0h) ........ 41 4.4.6 Local to PCI Doorbell Register (PCI 64h) (LOC E4h) ........ 41 4.4.7 Interrupt Control/Status (PCI 68h) (LOC E8h) .......... 42 4.4.8 EEPROM Control, PCI Command Codes, User I/O Control, Init Control Register (PCI 6Ch) (LOC ECh)... 43 4.4.9 PCI Configuration ID Register (PCI 70h) (LOC F0h)......... 43 5. SECTION 5 - PIN DESCRIPTION............ 44 5.1 PIN SUMMARY ... 44 6. SECTION 6 - ELECTRICAL AND TIMING SPECIFICATIONS .......... 56
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Version 1.0
Section C
PCI9060ES
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