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Part: SAA7111AH/02
Category:
Multimedia
-> Video
-> Decoders
Description: SAA7111A; Enhanced Video Input Processor (EVIP);; Package: SOT314-2 (LQFP64)
Company: Philips Semiconductors
Datasheet: Download SAA7111AH/02 datasheet File size : 2565 kB
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Datasheet text preview:
INTEGRATED CIRCUITS
DATA SHEET
SAA7111A Enhanced Video Input Processor (EVIP)
Product specification Supersedes data of 1997 May 26 File under Integrated Circuits, IC22 1998 May 15
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
CONTENTS 1 2 3 4 5 6 7 8 8.1 8.2 8.2.1 8.2.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.13.1 9 9.1 9.2 10 11 12 13 14 14.1 14.2 15 16 16.1 17 17.1 17.2 FEATURES APPLICATIONS GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Analog input processing Analog control circuits Clamping Gain control Chrominance processing Luminance processing RGB matrix VBI-data bypass VPO-bus (digital outputs) Reference signals HREF, VREF and CREF Synchronization Clock generation circuit Power-on reset and CE input RTCO output The Line-21 text slicer Suggestions for I2C-bus interface of the display software reading line-21 data BOUNDARY-SCAN TEST Initialization of boundary-scan circuit Device identification codes GAIN CHARTS LIMITING VALUES CHARACTERISTICS TIMING DIAGRAMS CLOCK SYSTEM Clock generation circuit Power-on control OUTPUT FORMATS APPLICATION INFORMATION Layout hints I2C-BUS DESCRIPTION I2C-bus format I2C-bus detail 17.2.1 17.2.2 17.2.3 17.2.4 17.2.5 17.2.6 17.2.7 17.2.8 17.2.9 17.2.10 17.2.11 17.2.12 17.2.13 17.2.14 17.2.15 17.2.16 17.2.17 17.2.18 17.2.19 17.2.20 17.2.21 17.2.22 17.2.23 17.2.24 17.2.25 18 18.1 18.2 18.3 18.4 19 20 21 21.1 21.2 21.3 21.4 22 23 24
SAA7111A
Subaddress 00 Subaddress 02 Subaddress 03 Subaddress 04 Subaddress 05 Subaddress 06 Subaddress 07 Subaddress 08 Subaddress 09 Subaddress 0A Subaddress 0B Subaddress 0C Subaddress 0D Subaddress 0E Subaddress 10 Subaddress 11 Subaddress 12 Subaddress 13 Subaddress 15 Subaddress 16 Subaddress 17 Subaddress 1A (read-only register) Subaddress 1B (read-only register) Subaddress 1C (read-only register) Subaddress 1F (read-only register) FILTER CURVES Anti-alias filter curve TUF-block filter curve Luminance filter curves Chrominance filter curves I2C-BUS START SET-UP PACKAGE OUTLINES SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
1998 May 15
2
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
1 FEATURES
SAA7111A
· Four analog inputs, internal analog source selectors, e.g. 4 × CVBS or 2 × Y/C or (1 × Y/C and 2 × CVBS) · Two analog preprocessing channels · Fully programmable static gain for the main channels or automatic gain control for the selected CVBS or Y/C channel · Switchable white peak control · Two built-in analog anti-aliasing filters · Two 8-bit video CMOS analog-to-digital converters · On-chip clock generator · Line-locked system clock frequencies · Digital PLL for horizontal-sync processing and clock generation · Requires only one crystal (24.576 MHz) for all standards · Horizontal and vertical sync detection · Automatic detection of 50 and 60 Hz field frequency, and automatic switching between PAL and NTSC standards · Luminance and chrominance signal processing for PAL BGHI, PAL N, PAL M, NTSC M, NTSC N, NTSC 4.43, NTSC-Japan and SECAM · User programmable luminance peaking or aperture correction · Cross-colour reduction for NTSC by chrominance comb filtering · PAL delay line for correcting PAL phase errors · Real time status information output (RTCO) · Brightness Contrast Saturation (BCS) control on-chip · The YUV (CCIR-601) bus supports a data rate of: 864 × fH = 13.5 MHz for 625 line sources 858 × fH = 13.5 MHz for 525 line sources. · Data output streams for 16, 12 or 8-bit width with the following formats: YUV 4 : 1 : 1 (12-bit) YUV 4 : 2 : 2 (16-bit) YUV 4 : 2 : 2 (CCIR-656) (8-bit) RGB (5, 6, and 5) (16-bit) with dither RGB (8, 8, and 8) (24-bit) with special application. 2 APPLICATIONS · Desktop/Notebook (PCMCIA) video · Multimedia · Digital television · Image processing · Video phone · Intercast. · Odd/even field identification by a non interlace CVBS input signal · Fix level for RGB output format during horizontal blanking · 720 active samples per line on the YUV bus · One user programmable general purpose switch on an output pin · Built-in line-21 text slicer · A 27 MHz Vertical Blanking Interval (VBI) data bypass programmable by I2C-bus for INTERCAST applications · Power-on control · Two via I2C-bus switchable outputs for the digitized CVBS or Y/C input signals AD1 (7 to 0) and AD2 (7 to 0) · Chip enable function (reset for the clock generator and power save mode up from chip version 3) · Compatible with memory-based features (line-locked clock) · Boundary scan test circuit complies with the `IEEE Std. 1149.1 - 1990' (ID-Code = 0 F111 02 B) · I2C-bus controlled (full read-back ability by an external controller) · Low power (<0.5 W), low voltage (3.3 V), small package (LQFP64) · 5 V tolerant digital I/O ports.
1998 May 15
3
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