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Part: SAA7108E
Category:
Description: SAA7108E; SAA7109E; Pc-codec
Company: Philips Semiconductors
Datasheet: Download SAA7108E datasheet File size : 2565 kB
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INTEGRATED CIRCUITS
DATA SHEET
SAA7108E; SAA7109E PC-CODEC
Product specification File under Integrated Circuits, IC22 2001 Dec 12
Philips Semiconductors
Product specification
PC-CODEC
CONTENTS 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.18 9 9.1 9.2 9.3 9.4 9.5 9.6 10 10.1 10.2 FEATURES Video decoder Video scaler Video encoder Common features APPLICATIONS GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAMS PINNING FUNCTIONAL DESCRIPTION OF DIGITAL VIDEO ENCODER PART Reset conditions Input formatter RGB LUT Cursor insertion RGB Y-CB-CR matrix Horizontal scaler Vertical scaler and anti-flicker filter FIFO Border generator Oscillator and Discrete Time Oscillator (DTO) Low-pass Clock Generation Circuit (CGC) Encoder RGB processor Triple DAC Timing generator I2C-bus interface Programming the graphics acquisition scaler of the video encoder Input levels and formats FUNCTIONAL DESCRIPTION OF DIGITAL VIDEO DECODER PART Decoder Decoder output formatter Scaler VBI data decoder and capture (subaddresses 40H to 7FH) Image port output formatter (subaddresses 84H to 87H) Audio clock generation (subaddresses 30H to 3FH) INPUT/OUTPUT INTERFACES AND PORTS OF DIGITAL VIDEO DECODER PART Analog terminals Audio clock signals 2 10.3 10.4 10.5 10.6 10.7 11 11.1 11.2 12 13 14 15 16 16.1 16.2 17 17.1 17.2 18 18.1 18.2 19 19.1 19.2 19.3 19.4 20 21 21.1 21.2 21.3 21.4 21.5 22 23 24 25
SAA7108E; SAA7109E
Clock and real-time synchronization signals Video expansion port (X port) Image port (I port) Host port for 16-bit extension of video data I/O (H port) Basic input and output timing diagrams I port and X port BOUNDARY SCAN TEST Initialization of boundary scan circuit Device identification codes LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS OF THE DIGITAL VIDEO ENCODER PART CHARACTERISTICS OF THE DIGITAL VIDEO DECODER PART TIMING Digital video encoder part Digital video decoder part APPLICATION INFORMATION Analog output voltages Suggestions for a board layout I2C-BUS DESCRIPTION Digital video encoder part Digital video decoder part PROGRAMMING START SET-UP OF DIGITAL VIDEO DECODER PART Decoder part Audio clock generation part Data slicer and data type control part Scaler and interfaces PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
2001 Dec 12
Philips Semiconductors
Product specification
PC-CODEC
1 1.1 FEATURES Video decoder
SAA7108E; SAA7109E
· Six analog inputs, internal analog source selectors, e.g. 6 × CVBS or (2 × Y/C and 2 × CVBS) or (1 × Y/C and 4 × CVBS) · Two analog preprocessing channels in differential CMOS style for best S/N-performance · Fully programmable static gain or Automatic Gain Control (AGC) for the selected CVBS or Y/C channel · Switchable white peak control · Two built-in analog anti-aliasing filters · Two 9-bit video CMOS Analog-To-Digital Converters (ADCs), digitized CVBS or Y/C signals are available on the IPD (Image Port Data) port under I2C-bus control · On-chip clock generator · Line-locked system clock frequencies · Digital PLL for horizontal sync processing and clock generation, horizontal and vertical sync detection · Requires only one crystal (either 24.576 MHz or 32.11 MHz) for all standards · Automatic detection of 50 and 60 Hz field frequency, and automatic switching between PAL and NTSC standards · Luminance and chrominance signal processing for PAL BGHI, PAL N, combination PAL N, PAL M, NTSC M, NTSC-Japan, NTSC N, NTSC 4.43 and SECAM · User programmable luminance peaking or aperture correction · Cross-colour reduction for NTSC by chrominance comb filtering · PAL delay line for correcting PAL phase errors · Brightness Contrast Saturation (BCS) and hue control on-chip · Two multi functional real-time output pins controlled by I2C-bus · Multi-standard VBI data slicer decoding World Standard Teletext (WST), North-American Broadcast Text System (NABTS), Closed Caption (CC), Wide Screen Signalling (WSS), Video Programming System (VPS), Vertical Interval Time Code (VITC) variants (EBU/SMPTE) etc. · Standard ITU 656 Y-CB-CR 4 : 2 : 2 format (8-bit) on IPD output bus · Enhanced ITU 656 output format on IPD output bus containing: active video raw CVBS data for INTERCAST applications (27 MHz data rate) decoded VBI data · Detection of copy protected input signals according to the macrovision standard. Can be used to prevent unauthorized recording of pay-TV or video tape signals. 1.2 Video scaler
· Both up and downscaling · Conversion to square pixel format · NTSC to 288 lines (video phone) · Phase accuracy better than 1/64 pixel or line, horizontally or vertically · Independent scaling definitions for odd and even fields · Anti-alias filter for horizontal scaling · Provides output as scaled active video raw CVBS data for INTERCAST, WAVE-PHORE, POPCON applications or general VBI data decoding (27 MHz or sample rate converted) · Local video output for Y-CB-CR 4 : 2 : 2 format (VMI, VIP, ZV). 1.3 Video encoder
· Digital PAL/NTSC encoder with integrated high quality scaler and anti-flicker filter for TV output from a PC · 27 MHz crystal-stable subcarrier generation · Maximum graphics pixel clock 45 MHz at double edged clocking, synthesized on-chip or from external source · Up to 800 × 600 graphics data at 60 Hz or 50 Hz with programmable underscan range · Three Digital-to-Analog Converters (DACs) at 27 MHz sample rate for CVBS (BLUE, CB), VBS (GREEN, CVBS) and C (RED, CR) (signals in parenthesis are optional); all at 10-bit resolution
2001 Dec 12
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