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Part: SAA7104H
Category:
Multimedia
-> Video
-> Encoders
Description: Digital Video Encoder<<<>>><<<>>>an Advanced Next-generation Video Encoder Which Converts PC Graphics Data at Maximum 1280 X 1024 Resolution (optionally 1920 X 1080 Interlaced) to Pal (50 Hz) or NTSC (60 Hz) Video Signals. A Programmable Scaler And Anti-flicker Filter (maximum 5 Lines) Ensures Properly Sized And Flicker-free TV Display as CVBS or S-video Output. <<<>>><<<>>>Alternatively, The Three Digital-to-analog Converters (DACs) CAN Output RGB Signals Together With a TTL Composite SYNC to Feed Scart Connectors. <<<>>><<<>>>When The Scaler/interlacer is Bypassed, a Second Vga Monitor CAN be Connected to The RGB Outputs And Separate H And V-syncs as Well, Thereby Serving as an Auxiliary Monitor at Maximum 1280 X 1024 Resolution/60 HZ (PIXCLK < 85 MHz). Alternatively This Port CAN Provide Y, PB And PR Signals For HDTV Monitors. <<<>>><<<>>>The Device Includes a Sync/clock Generator And On-chip DACs. <<<>>><<<>>>All Inputs Intended to Interface to The Host Graphics Controller Are Designed For Low-voltage Signals Between Down to 1.1 V And up to 3.6 V. <<<>>><<<>>> <<<>>> Features Digital Pal/ntsc Encoder With Integrated High Quality Scaler And Anti-flicker Filter For TV Output From a PC <<<>>>Supports Intel Digital Video Out (DVO) Low Voltage Interfacing to Graphics Controller <<<>>>27 MHZ Crystal-stable Subcarrier Generation <<<>>>Maximum Graphics Pixel Clock 85 MHZ at Double Edged Clocking, Synthesized On-chip or From External Source <<<>>>Programmable Assignment of Clock Edge to Bytes (in Double Edged Mode) <<<>>>Synthesizable Pixel Clock (PIXCLK) With Minimized Output Jitter, CAN be Used as Reference Clock For The Vgc, as Well) <<<>>>PIXCLK Output And Bi-phase Pixclk Input (VGC Clock Loop-through Possible) <<<>>>Hot-plug Detection Through Dedicated Interrupt Pin <<<>>>Supported Vga Resolutions For Pal or NTSC Legacy Video Output up to 1280 X 1024 Graphics Data at 60 or 50 HZ Frame Rate <<<>>>Supported Vga Resolutions For HDTV Output up to 1920 X 1080 Interlaced Graphics Data at 60 or 50 HZ Frame Rate <<<>>>Three Digital-to-analog Converters (DACs) For CVBS (BLUE, CB), VBS (GREEN, CVBS) And C (RED, CR) at 27 MHZ Sample Rate (signals in Parenthesis Are Optionally), All at 10-bit Resolution <<<>>>Non-interlaced Cb-y-cr or RGB Input at Maximum 4 : 4 : 4 Sampling <<<>>>Downscaling And Upscaling From 50 to 400 Pct. <<<>>>Optional Interlaced Cb-y-cr Input of Digital Versatile Disk (DVD) Signals <<<>>>Optional Non-interlaced RGB Output to Drive Second Vga Monitor (bypass Mode, Maximum 85 MHz) <<<>>>3 X 256 Bytes RGB Look-up Table (LUT) <<<>>>Support For Hardware Cursor <<<>>>HDTV up to 1920 X 1080 Interlaced And 1280 X 720 Progressive, Including 3-level SYNC Pulses <<<>>>Programmable Border Colour of Underscan Area <<<>>>Programmable 5 Line Anti-flicker Filter <<<>>>On-chip 27 MHZ Crystal Oscillator (3rd-harmonic or Fundamental 27 MHZ Crystal) <<<>>>Fast i C-bus Control Port (400 KHz) <<<>>>Encoder CAN be Master or Slave <<<>>>Adjustable Output Levels For The DACs <<<>>>Programmable Horizontal And Vertical Input Synchronization Phase <<<>>>Programmable Horizontal SYNC Output Phase <<<>>>Internal Colour Bar Generator (CBG) <<<>>>Optional Support of Various Vertical Blanking Interval (VBI) Data Insertion <<<>>>Macrovision (1) Pay-per-view Copy Protection System Rev. 7.01, Rev. 6.1 And Rev. 1.03 (525p) as Option; This Applies to The SAA7104H Only. The Device is Protected BY Usa Patent Numbers 4631603, 4577216 And 4819098 And Other Intellectual Property Rights. Use of The Macrovision Anti-copy Process in The Device is Licensed For Non-commercial Home Use Only. Reverse Engineering or Disassembly is Prohibited. Please Contact Your Nearest Philips Semiconductors Sales Office For More Information. <<<>>>Optional Cross-colour Reduction For Pal And NTSC CVBS Outputs <<<>>>Power-save Modes <<<>>>Joint Test Action Group (JTAG) Boundary Scan Test <<<>>>Monolithic CMOS 3.3 V Device, 5 V Tolerant I/os <<<>>>QFP64 Package.
Company: Philips Semiconductors
Datasheet: Download SAA7104H datasheet File size : 2565 kB
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INTEGRATED CIRCUITS
DATA SHEET
SAA7104H; SAA7105H Digital video encoder
Product specification 2004 Mar 04
Philips Semiconductors
Product specification
Digital video encoder
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 7.24 7.25 FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Reset conditions Input formatter RGB LUT Cursor insertion RGB Y-CB-CR matrix Horizontal scaler Vertical scaler and anti-flicker filter FIFO Border generator Oscillator and Discrete Time Oscillator (DTO) Low-pass Clock Generation Circuit (CGC) Encoder RGB processor Triple DAC HD data path Timing generator Pattern generator for HD sync pulses I2C-bus interface Power-down modes Programming the SAA7104H; SAA7105H Input levels and formats Bit allocation map I2C-bus format Slave receiver Slave transmitter 8 8.1 8.2 9 10 11 11.1 12 12.1 12.2 12.3 13 14 14.1 14.2 14.3 14.4 14.5 15 16 17 18
SAA7104H; SAA7105H
BOUNDARY SCAN TEST Initialization of boundary scan circuit Device identification codes LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS Teletext timing APPLICATION INFORMATION Reconstruction filter Analog output voltages Suggestions for a board layout PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
2004 Mar 04
2
Philips Semiconductors
Product specification
Digital video encoder
1 FEATURES
SAA7104H; SAA7105H
· Digital PAL/NTSC encoder with integrated high quality scaler and anti-flicker filter for TV output from a PC · Supports Intel® Digital Video Out (DVO) low voltage interfacing to graphics controller · 27 MHz crystal-stable subcarrier generation · Maximum graphics pixel clock 85 MHz at double edged clocking, synthesized on-chip or from external source · Programmable assignment of clock edge to bytes (in double edged mode) · Synthesizable pixel clock (PIXCLK) with minimized output jitter, can be used as reference clock for the VGC, as well) · PIXCLK output and bi-phase PIXCLK input (VGC clock loop-through possible) · Hot-plug detection through dedicated interrupt pin · Supported VGA resolutions for PAL or NTSC legacy video output up to 1280 × 1 024 graphics data at 60 or 50 Hz frame rate · Supported VGA resolutions for HDTV output up to 1 920 × 1 080 interlaced graphics data at 60 or 50 Hz frame rate · Three Digital-to-Analog Converters (DACs) for CVBS (BLUE, CB), VBS (GREEN, CVBS) and C (RED, CR) at 27 MHz sample rate (signals in parenthesis are optionally), all at 10-bit resolution · Non-interlaced CB-Y-CR or RGB input at maximum 4 : 4 : 4 sampling · Downscaling and upscaling from 50 to 400% · Optional interlaced CB-Y-CR input of Digital Versatile Disk (DVD) signals · Optional non-interlaced RGB output to drive second VGA monitor (bypass mode, maximum 85 MHz) · 3 × 256 bytes RGB Look-Up Table (LUT) · Support for hardware cursor · HDTV up to 1920 × 1 080 interlaced and 1280 × 720 progressive, including 3-level sync pulses · Programmable border colour of underscan area · Programmable 5 line anti-flicker filter · On-chip 27 MHz crystal oscillator (3rd-harmonic or fundamental 27 MHz crystal) · Fast I2C-bus control port (400 kHz) · Encoder can be master or slave · Adjustable output levels for the DACs · Programmable horizontal and vertical input synchronization phase · Programmable horizontal sync output phase · Internal Colour Bar Generator (CBG) · Optional support of various Vertical Blanking Interval (VBI) data insertion · MacrovisionTM(1) Pay-per-View copy protection system rev. 7.01, rev. 6.1 and rev. 1.03 (525p) as option; this applies to the SAA7104H only. The device is protected by USA patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anti-copy process in the device is licensed for non-commercial home use only. Reverse engineering or disassembly is prohibited. Please contact your nearest Philips Semiconductors sales office for more information. · Optional cross-colour reduction for PAL and NTSC CVBS outputs · Power-save modes · Joint Test Action Group (JTAG) boundary scan test · Monolithic CMOS 3.3 V device, 5 V tolerant I/Os · QFP64 package.
(1) MacrovisionTM is a trademark of the Macrovision Corporation.
2004 Mar 04
3
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