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Part: SAA2502H
Category:
Description: SAA2502; ISO/mpeg Audio Source Decoder
Company: Philips Semiconductors
Datasheet: Download SAA2502H datasheet File size : 2565 kB
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INTEGRATED CIRCUITS
DATA SHEET
SAA2502 ISO/MPEG Audio Source Decoder
Preliminary specification Supersedes data of 1997 Apr 18 File under Integrated Circuits, IC01 1997 Nov 17
Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.3 7.3.1 7.3.2 7.3.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 7.4.8 7.4.9 7.5 7.5.1 7.5.2 7.5.3 7.6 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.6.6 8 8.1 8.1.1 8.1.2 8.1.3 8.1.4 FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Basic functionality Clock generator module External sample clock Free running internal sample clock Locked internal sample clock Limited sampling frequency support for internal sampling clocks Input interface module Master input mode Slave input mode Buffer controlled input mode Decoder core Frame synchronization to input data streams Master input mode bit rate generation Sample clock generation Decoder precision Scale factor CRC protection Handling of errors in the coded input data Dynamic range compression Baseband audio processing Decoder latency time Output interface module I2S output SPIDF output Bit serial analog output Control interface module Resetting Interrupts Microcontroller interface Initialization Transfer protocols Local registers APPENDIX L3 interface specification Introduction Example of a data transfer Timing requirements Timing 9 10 11 11.1 12 13 14 14.1 14.2 14.3 14.4 15 16 LIMITING VALUES DC CHARACTERISTICS AC CHARACTERISTICS
SAA2502
Host interface: CDATA, CCLK and CMODE APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS
1997 Nov 17
2
Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
1 FEATURES 2 APPLICATIONS
SAA2502
· Low sampling frequency decoding possibilities (24 kHz, 22.05 kHz and 16 kHz) of MPEG2 are supported · A variety of output formats are supported: I2S, SPDIF and 256 or more times oversampled bit serial analog stereo · Automatic internal dynamic range compression algorithm using programmable compression parameters · Non byte-aligned coded input data is handled · Built-in provisions to generate high quality sampling clocks for all six supported sampling frequencies; these sampling clocks may locked to an external PLL to support an extensive list of input data reference clock frequencies · Bit-rate and sampling-rate settings may be overruled by the microcontroller while the SAA2502 is trying to establish frame synchronization · Input interface mode which requests data based on input buffer content, enables the handling of variable bit-rate input streams and input data offered in (fixed length) bursts · An interrupt output pin which can generate interrupt requests at the occurrence of various events; consequently polling by the microcontroller is not needed in most situations · L3 and the I2C-bus microcontroller interface protocols are supported · The control interface is always fully operational (also while STOP is asserted) · CRC protection of scale factors is provided for all supported sample frequencies. 4 ORDERING INFORMATION
· Astra Digital Radio (ADR) · Digital Audio Broadcast (DAB) · Digital Versatile Disc (DVD) · Digital Video Broadcast (DVB) · General purpose MPEG2 audio decoding. 3 GENERAL DESCRIPTION
The SAA2502 is a second generation ISO/MPEG audio source decoder. The device specification has been enhanced with respect to the SAA2500 and SAA2501 ICs and therefore it offers in principle all features of its predecessors. It supports layer I and II of MPEG1 and the MPEG2 requirements for a stereo decoder.
PACKAGE TYPE NUMBER NAME SAA2502H QFP44 DESCRIPTION plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm VERSION SOT307-2
1997 Nov 17
3
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