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Part: PHP60N06LT
Category:
Discrete
-> Transistors
-> FETs (Field Effect Transistors)
-> MOSFETs
-> N-Channel
Description: PHP60N06LT/PHB60N06LT; Trenchmos (tm) Transistor Logic Level Fet
Company: Philips Semiconductors
Datasheet: Download PHP60N06LT datasheet File size : 82 kB
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Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
FEATURES
· 'Trench' technology · Very low on-state resistance · Fast switching · Stable off-state characteristics · High thermal cycling performance · Low thermal resistance
PHP60N06LT, PHB60N06LT
SYMBOL
d
QUICK REFERENCE DATA VDSS = 55 V ID = 58 A
g s
RDS(ON) 20 m (VGS = 5 V) RDS(ON) 18 m (VGS = 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using 'trench' technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. The PHP60N06LT is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB60N06LT is supplied in the SOT404 surface mounting package.
PINNING
PIN 1 2 3 tab gate drain1 source drain DESCRIPTION
SOT78 (TO220AB)
tab
SOT404
tab
2
1 23
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 °C to 175°C Tj = 25 °C to 175°C; RGS = 20 k Tmb = 25 °C Tmb = 100 °C Tmb = 25 °C Tmb = 25 °C MIN. - 55 MAX. 55 55 ± 13 58 40 232 150 175 UNIT V V V A A A W °C
1 It is not possible to make connection to pin 2 of the SOT404 package. January 1998 1 Rev 1.300
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
THERMAL RESISTANCES
SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS
PHP60N06LT, PHB60N06LT
TYP. -
MAX. 1.0 -
UNIT K/W K/W K/W
SOT78 package, in free air SOT404 package, pcb mounted, minimum footprint
60 50
ESD LIMITING VALUE
SYMBOL PARAMETER VC Electrostatic discharge capacitor voltage, all pins CONDITIONS Human body model (100 pF, 1.5 k) MIN. MAX. 2 UNIT kV
ELECTRICAL CHARACTERISTICS
Tj= 25°C unless otherwise specified SYMBOL PARAMETER V(BR)DSS V(BR)GSS VGS(TO) RDS(ON) gfs IGSS IDSS Qg(tot) Qgs Qgd td on tr td off tf Ld Ld Ls Ciss Coss Crss Drain-source breakdown voltage Gate-source breakdown voltage Gate threshold voltage Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA; IG = ±1 mA; VDS = VGS; ID = 1 mA Tj = 175°C Tj = -55°C VGS = 5 V; ID = 25 A VGS = 10 V; ID = 25 A Tj = 175°C Forward transconductance VDS = 25 V; ID = 25 A Gate source leakage current VGS = ±5 V; VDS = 0 V Tj = 175°C Zero gate voltage drain current Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance VDS = 55 V; VGS = 0 V; Tj = 175°C ID = 50 A; VDD = 44 V; VGS = 5 V Tj = -55°C MIN. 55 50 10 1.0 0.5 20 TYP. MAX. UNIT 1.5 15 16 52 0.02 0.05 37 10 17 28 110 95 70 3.5 4.5 7.5 1800 350 170 2.0 2.3 20 18 42 1 20 10 500 40 160 135 90 2400 420 235 V V V V V V m m m S µA µA µA µA nC nC nC ns ns ns ns nH nH nH pF pF pF
VDD = 30 V; ID = 25 A; VGS = 5 V; RG = 10 Resistive load Measured from tab to centre of die Measured from drain lead to centre of die (SOT78 package only) Measured from source lead to source bond pad VGS = 0 V; VDS = 25 V; f = 1 MHz
January 1998
2
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
PHP60N06LT, PHB60N06LT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25°C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 25 A; VGS = 0 V IF = 40 A; VGS = 0 V IF = 40 A; -dIF/dt = 100 A/µs; VGS = -10 V; VR = 30 V TYP. MAX. UNIT 0.95 1.0 47 0.15 58 232 1.2 A A V V ns µC
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER WDSS CONDITIONS MIN. MAX. 110 UNIT mJ Drain-source non-repetitive ID = 45 A; VDD 25 V; VGS = 5 V; unclamped inductive turn-off RGS = 50 ; Tmb = 25 °C energy
120 110 100 90 80 70 60 50 40 30 20 10 0
PD%
Normalised Power Derating
120 110 100 90 80 70 60 50 40 30 20 10 0
ID%
Normalised Current Derating
0
20
40
60
80 100 Tmb / C
120
140
160
180
0
20
40
60
80 100 Tmb / C
120
140
160
180
Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 °C = f(Tmb)
Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 °C = f(Tmb); conditions: VGS 5 V
January 1998
3
Rev 1.300
Others parts begin by ph
PH-1 PH-2 PH-3 PH-4 PH-5
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