|
|
Part: PHP50N03LT
Category:
Discrete
-> Transistors
-> FETs (Field Effect Transistors)
-> MOSFETs
-> Power MOSFETs
-> N-Channel
Description: PHB50N03LT; PHD50N03LT; PHP50N03LT; N-channel Trenchmos (tm) Transistor Logic Level Fet
Company: Philips Semiconductors
Datasheet: Download PHP50N03LT datasheet File size : 82 kB
Request For quote: Find where to buy PHP50N03LT
Datasheet text preview:
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor Logic level FET
FEATURES
· 'Trench' technology · Very low on-state resistance · Fast switching · High thermal cycling performance · Low thermal resistance · Logic level compatible
PHP50N03LT, PHB50N03LT PHD50N03LT
QUICK REFERENCE DATA
d
SYMBOL
VDSS = 25 V ID = 48 A RDS(ON) 16 m (VGS = 10 V) RDS(ON) 21 m (VGS = 5 V)
g
s
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using 'trench' technology. Applications:· High frequency computer motherboard d.c. to d.c. converters · High current switching The PHP50N03LT is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB50N03LT is supplied in the SOT404 (D2PAK) surface mounting package. The PHD50N03LT is supplied in the SOT428 (DPAK)surface mounting package.
PINNING
PIN 1 2 3 tab DESCRIPTION gate drain 1 source
SOT78 (TO220AB)
tab
SOT404 (D2PAK)
tab
SOT428 (DPAK)
tab
2
1 23
2
1
3
1
3
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS VGSM ID IDM Ptot Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage (DC) Gate-source voltage (pulse peak value) Drain current (DC) Drain current (pulse peak value) Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 °C to 175°C Tj = 25 °C to 175°C; RGS = 20 k Tj 150°C Tmb = 25 °C Tmb = 100 °C Tmb = 25 °C Tmb = 25 °C MIN. - 55 MAX. 25 25 ± 15 ± 20 48 34 180 86 175 UNIT V V V V A A A W °C
1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages. October 1999 1 Rev 1.800
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor Logic level FET
THERMAL RESISTANCES
SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS
PHP50N03LT, PHB50N03LT PHD50N03LT
MIN. -
TYP. MAX. UNIT 60 50 1.75 K/W K/W K/W
SOT78 package, in free air SOT404 and SOT428 packages, pcb mounted, minimum footprint
-
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER WDSS CONDITIONS MIN. MAX. 60 UNIT mJ Drain-source non-repetitive ID = 25 A; VDD 15 V; unclamped inductive turn-off VGS = 5 V; RGS = 50 ; Tmb = 25 °C energy
ELECTRICAL CHARACTERISTICS
Tj= 25°C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) RDS(ON) Drain-source breakdown voltage Gate threshold voltage Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55°C VDS = VGS; ID = 1 mA Tj = 175°C Tj = -55°C VGS = 10 V; ID = 25 A VGS = 10 V; ID = 25 A (SOT428 package) VGS = 5 V; ID = 25 A VGS = 5 V; ID = 25 A; Tj = 175°C Forward transconductance VDS = 25 V; ID = 25 A Zero gate voltage drain VDS = 25 V; VGS = 0 V; current Tj = 175°C Gate source leakage current VGS = ±5 V; VDS = 0 V Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance ID = 50 A; VDD = 15 V; VGS = 5 V MIN. 25 22 1 0.5 8 TYP. MAX. UNIT 1.5 13 15 18 27 0.05 10 17 7.6 11 6.4 62 50 30 3.5 4.5 7.5 1050 330 220 2 2.3 16 18 21 39 10 500 100 12 75 75 45 V V V V V m m m m S µA µA nA nC nC nC ns ns ns ns nH nH nH pF pF pF
gfs IDSS IGSS Qg(tot) Qgs Qgd td on tr td off tf Ld Ld Ls Ciss Coss Crss
VDD = 15 V; ID = 25 A; VGS = 10 V; RG = 5 Resistive load Measured tab to centre of die Measured from drain lead to centre of die (SOT78 package only) Measured from source lead to source bond pad VGS = 0 V; VDS = 25 V; f = 1 MHz
October 1999
2
Rev 1.800
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor Logic level FET
PHP50N03LT, PHB50N03LT PHD50N03LT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25°C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 25 A; VGS = 0 V IF = 40 A; VGS = 0 V IF = 20 A; -dIF/dt = 100 A/µs; VGS = 0 V; VR = 25 V TYP. MAX. UNIT 0.95 1.05 100 0.13 48 180 1.2 A A V ns µC
Normalised Power Derating, PD (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 175
1000
Peak Pulsed Drain Current, IDM (A)
RDS(on) = VDS/ ID 100 tp = 10 us
100 us
10 D.C.
1 ms 10 ms 100 ms
1 1 10 Drain-Source Voltage, VDS (V) 100
Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 °C = f(Tmb)
Fig.3. Safe operating area ID & IDM = f(VDS); IDM single pulse; parameter tp
Transient thermal impedance, Zth j-mb (K/W)
Normalised Current Derating, ID (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 175
10
1
D = 0.5 0.2 0.1 0.05 0.02 P D D = tp/T
0.1
tp
single pulse 0.01 1E-06 1E-05 1E-04 1E-03 Pulse width, tp (s) 1E-02
T 1E-01 1E+00
Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 °C = f(Tmb); conditions: VGS 5 V
Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T
October 1999
3
Rev 1.800
Others parts begin by ph
PH-1 PH-2 PH-3 PH-4 PH-5
|
|
|
