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Part: PHN1011
Category:
Discrete
-> Transistors
-> FETs (Field Effect Transistors)
-> MOSFETs
-> N-Channel
Description: PHN1011; Trenchmos (tm) Transistor Logic Level Fet
Company: Philips Semiconductors
Datasheet: Download PHN1011 datasheet File size : 117 kB
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Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
FEATURES
· 'Trench' technology · Low on-state resistance · Fast switching · High thermal cycling performance · Low-profile surface mount package · Logic level compatible
PHN1011
SYMBOL
d
QUICK REFERENCE DATA VDSS = 25 V ID = 11 A
g
RDS(ON) 11 m (VGS = 10 V) RDS(ON) 13.5 m (VGS = 5 V)
s
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a surface mounting plastic package using 'trench' technology. The combination of very low on-state resistance and low switching losses make this device the optimum choice in high speed computer motherboard d.c. to d.c. converters. The PHN1011 is supplied in the SOT96-1 (SO8) surface mounting package
PINNING
PIN 1-3 4 5-8 DESCRIPTION
SOT96-1 (SO8)
8 7 6 5
source gate drain
pin 1 index
1
2
3
4
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDSS VDGR VGS VGSM ID IDM Ptot Tj, Tstg PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage (DC) Gate-source voltage (pulse peak value) Drain current (tp 10 s) Drain current (pulse peak value) Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 °C to 150°C Tj = 25 °C to 150°C; RGS = 20 k Ta = 25 °C Ta = 70 °C Ta = 25 °C Ta = 25 °C Ta = 70 °C MIN. - 55 MAX. 25 25 ± 15 ± 20 11 9 44 2.5 1.6 150 UNIT V V V V A A A W W °C
THERMAL RESISTANCES
SYMBOL PARAMETER Rth j-a Rth j-a Thermal resistance junction to ambient Thermal resistance junction to ambient CONDITIONS Surface mounted, FR4 board, t 10 sec Surface mounted, FR4 board TYP. 150 MAX. 50 UNIT K/W K/W
June 1999
1
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
ELECTRICAL CHARACTERISTICS
Tj= 25°C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) RDS(ON) gfs IGSS IDSS Qg(tot) Qgs Qgd td on tr td off tf Ld Ls Ciss Coss Crss Drain-source breakdown voltage Gate threshold voltage Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55°C VDS = VGS; ID = 1 mA Tj = 150°C Tj = -55°C VGS = 10 V; ID = 10 A VGS = 5 V; ID = 5 A VGS = 5 V; ID = 5 A; Tj = 150°C Forward transconductance VDS = 25 V; ID = 10 A Gate source leakage current VGS = ±5 V; VDS = 0 V Zero gate voltage drain VDS = 25 V; VGS = 0 V; current Tj = 150°C Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance ID = 25 A; VDD = 15 V; VGS = 5 V MIN. 25 22 1 0.6 12 -
PHN1011
TYP. MAX. UNIT 1.5 9 11 36 10 0.05 26 6 9.4 7 50 82 59 1 3 1700 475 300 2 2.3 11 13.5 23 100 10 500 15 75 120 75 V V V V V m m m S nA µA µA nC nC nC ns ns ns ns nH nH pF pF pF
VDD = 15 V; ID = 25 A; VGS = 10 V; RG = 5 Resistive load Drain leads to centre of die Source leads to source bond pad VGS = 0 V; VDS = 20 V; f = 1 MHz
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25°C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS Ta = 25 °C, tp 10 s MIN. IF = 10 A; VGS = 0 V IF = 10 A; -dIF/dt = 100 A/µs; VGS = 0 V; VR = 25 V TYP. MAX. UNIT 0.95 83 0.1 11 44 1.2 A A V ns µC
June 1999
2
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
PHN1011
Normalised Power Derating, Ptot (%)
100 90 80 70 60 50 40 30 20 10 0 0 20 40 60 80 100 120 140 160
Ambient temperature, Ta (C)
100
Transient thermal impedance, Zth j-mb (K/W) D = 0.5 0.2
10 0.1 0.05 0.02 1 P D 0.1 single pulse D = tp/T
tp
T 0.01 1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01
Pulse width, tp (s)
Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 °C = f(Ta)
Fig.4. Transient thermal impedance. Zth j-a = f(t); parameter D = tp/T
Drain Current, ID (A) VGS = 10 V 45 4.5 V 3V 40 35 5V Tj = 25 C
Normalised Current Derating, ID (%)
50
120 100 80
30
2.8 V
60 40
25 2.6 V 20 15 2.4 V 2.2 V 5
20 0 0 20 40 60 80 100 120 140 160
10 2V 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Drain-Source Voltage, VDS (V) 1.6 1.8 2
0
Ambient temperature, Ta (C)
Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 °C = f(Ta); conditions: VGS 5 V
Peak Pulsed Drain Current, IDM (A) RDS(on) = VDS/ ID tp = 10 us 100 us 10 1 ms 10 ms 100 ms D.C.
Fig.5. Typical output characteristics, Tj = 25 °C. ID = f(VDS); parameter VGS
100
Drain-Source On Resistance, RDS(on) (Ohms) 0.1 2.2 V 0.09 0.08 0.07 0.06 2.8V 2.4 V 2.6 V Tj = 25 C
1
0.05 0.04
3V
0.1
0.03 0.02 0.01 10V 5V VGS =4.5 V
0.01 0.1 1 10 Drain-Source Voltage, VDS (V) 100
0 0 5 10 15 20 25 30 Drain Current, ID (A) 35 40 45 50
Fig.3. Safe operating area. Ta = 25 °C ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 °C. RDS(ON) = f(ID); parameter VGS
June 1999
3
Rev 1.100
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