|
|
Part: PHKD6N02LT
Category:
Discrete
-> Transistors
-> FETs (Field Effect Transistors)
-> MOSFETs
-> Power MOSFETs
Description: PHKD6N02LT; Dual Trenchmos (tm) Logic Level FET;; Package: SOT96-1 (SO8)
Company: Philips Semiconductors
Datasheet: Download PHKD6N02LT datasheet File size : 89 kB
Request For quote: Find where to buy PHKD6N02LT
Datasheet text preview:
PHKD6N02LT
Dual TrenchMOSTM logic level FET
M3D315
Rev. 02 -- 12 August 2003
Product data
1. Description
Dual N-channel enhancement mode field-effect transistors in a plastic surface mount package using TrenchMOSTM technology. Product availability: PHKD6N02LT in SOT96-1 (SO8).
2. Features
s s s s Low on-state resistance Logic level compatible Dual device Surface mount package.
3. Applications
s s s s DC-to-DC converters Notebook computers Por table appliances Batter y chargers.
4. Pinning information
Table 1: Pin 1 2 3 4 5, 6 7, 8 Pinning - SOT96-1 (SO8), simplified outline and symbol Description source1 (s1) gate1 (g1) source2 (s2) gate2 (g2) drain2 (d2) drain1 (d1)
1 Top view 4
MBK187
Simplified outline
8 5
Symbol
d1 d1 d2 d2
SOT96-1 (SO8)
s1
g
1
s2
g
2
MBK725
Philips Semiconductors
PHKD6N02LT
Dual TrenchMOSTM logic level FET
5. Quick reference data
Table 2: VDS ID Ptot Tj RDSon Quick reference data Conditions 25 °C Tj 150 °C Tsp = 25 °C Tsp = 25 °C VGS = 5 V; ID = 3 A VGS = 2.5 V; ID = 3 A
[1] Single device conducting.
[1]
Symbol Parameter drain-source voltage (DC) drain current (DC) total power dissipation junction temperature drain-source on-state resistance
Typ 16 25
Max 20 10.9 4.17 150 20 35
Unit V A W °C m m
6. Ordering information
Table 3: Ordering information Package Name PHKD6N02LT SO8 Description Plastic small outline package; 8 leads Version SOT96-1 Type number
7. Limiting values
Table 4: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM drain-source voltage (DC) drain-gate voltage (DC) gate-source voltage (DC) drain current (DC) peak drain current total power dissipation storage temperature junction temperature source (diode forward) current (DC) Tsp = 25 °C peak (diode forward) source current Tsp = 25 °C; tp 10 µs
[1] Single device conducting.
Conditions Tj = 25 to 150 °C Tj = 25 to 150 °C; RGS = 20 k Tsp = 25 °C; Figure 2 and 3 Tsp = 100 °C; Figure 2 Tsp = 25 °C; tp 100 µs; Figure 3 Tsp = 25 °C; Figure 1
[1] [1] [1]
Min -55 -55 -
Max 20 20 ±12 10.9 6.8 44 4.17 +150 +150 3.5 44
Unit V V V A A A W °C °C A A
Source-drain (reverse) diode
9397 750 10688
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 -- 12 August 2003
2 of 12
Philips Semiconductors
PHKD6N02LT
Dual TrenchMOSTM logic level FET
120 Pder (%) 80
03aa17
120 Ider (%) 80
03aa25
40
40
0 0 50 100 150 Tsp (°C) 200
0 0 50 100 150 200 Tsp (°C)
VGS 4.5 V
Pd e r
Pt o t = ---------------------- × 100 % P °
t o t ( 25 C )
ID I d e r = ------------------- × 100 % I °
D ( 25 C )
Fig 1. Normalized total power dissipation as a function of solder point temperature.
Fig 2. Normalized continuous drain current as a function of solder point temperature.
102
003aaa300
Limit RDSon = VDS/ID ID (A)
10
tp = 10 µs 100 µs 1 ms 10 ms
100 ms DC
1
10-1
10-2 10-1
1
10
VDS (V)
102
Tsp = 25 °C; IDM is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 10688
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 -- 12 August 2003
3 of 12
Others parts begin by ph
PH-1 PH-2 PH-3 PH-4 PH-5
|
|
|
