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Part: PHKD13N03LT
Category:
Discrete
-> Transistors
-> FETs (Field Effect Transistors)
-> MOSFETs
-> Power MOSFETs
Description: PHKD13N03LT; Dual Trenchmos (tm) Logic Level FET;; Package: SOT96-1 (SO8)
Company: Philips Semiconductors
Datasheet: Download PHKD13N03LT datasheet File size : 89 kB
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Datasheet text preview:
PHKD13N03LT
M3D315
Dual TrenchMOSTM logic level FET
Rev. 01 -- 23 June 2003 Product data
1. Product profile
1.1 Description
Dual N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOSTM technology. Product availability: PHKD13N03LT in SOT96-1 (SO8).
1.2 Features
s Low gate charge s Low on-state resistance s Surface mount package s Fast switching.
1.3 Applications
s Por table appliances s Lithium-ion battery chargers s Notebook computers s DC-to-DC converters.
1.4 Quick reference data
s VDS 30 V s Ptot 3.57 W s ID 10.4 A s RDSon 20 m
2. Pinning information
Table 1: Pin 1 2 3 4 5,6 7,8 Pinning - SOT96-1 (SO8), simplified outline and symbol Description source1 (s1) gate1 (g1) source2 (s2) gate2 (g2) drain2 (d2) drain1 (d1)
1 Top view 4
MBK187
Simplified outline
8 5
Symbol
d1 d1 d2 d2
SOT96-1 (SO8)
s1
g
1
s2
g
2
MBK725
Philips Semiconductors
PHKD13N03LT
Dual TrenchMOSTM logic level FET
3. Limiting values
Table 2: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM
[1]
Conditions 25 °C Tj 150 °C 25 °C Tj 150 °C; RGS = 20 k Tsp = 25 °C; VGS = 10 V; Figure 2 and 3 Tsp = 100 °C; VGS = 10 V; Figure 2 Tsp = 25 °C; pulsed; tp 10 µs; Figure 3 Tsp = 25 °C; Figure 1
[1] [1] [1]
Min -55 -55
[1] [1]
Max 30 30 ±20 10.4 6.6 42 3.57 +150 +150 3.2 42
Unit V V V A A A W °C °C A A
drain-source voltage (DC) drain-gate voltage (DC) gate-source voltage (DC) drain current (DC) peak drain current total power dissipation storage temperature junction temperature
Source-drain diode source (diode forward) current (DC) Tsp = 25 °C peak source (diode forward) current Tsp = 25 °C; pulsed; tp 10 µs
Single device conducting.
-
9397 750 11612
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 01 -- 23 June 2003
2 of 12
Philips Semiconductors
PHKD13N03LT
Dual TrenchMOSTM logic level FET
120 Pder (%) 80
03aa17
120 Ider (%) 80
03aa25
40
40
0 0 50 100 150 Tsp (°C) 200
0 0 50 100 150 200 Tsp (°C)
Pt o t P d e r = ---------------------- × 100 % P °
t o t ( 25 C )
VGS 5 V
ID I d e r = ------------------- × 100 % I °
D ( 25 C )
Fig 1. Normalized total power dissipation as a function of solder point temperature.
Fig 2. Normalized continuous drain current as a function of solder point temperature.
102
003aaa368
ID (A)
Limit RDSon = VDS/ID
tp = 10 µs
10
100 µs
1 ms 10 ms
1
DC 100 ms
10-1 10-1
1
10
VDS (V)
102
Tsp = 25 °C; IDM is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 11612
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 01 -- 23 June 2003
3 of 12
Others parts begin by ph
PH-1 PH-2 PH-3 PH-4 PH-5
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