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Part: PHK5NQ15T

Category:
 Discrete
   -> Transistors
     -> FETs (Field Effect Transistors)
       -> MOSFETs
         -> Power MOSFETs

Description: PHK5NQ15T; Trenchmos (tm) Standard Level FET;; Package: SOT96-1 (SO8)

Company: Philips Semiconductors

Datasheet: Download PHK5NQ15T datasheet     File size : 89 kB

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Datasheet text preview:
PHK5NQ15T
TrenchMOSTM standard level FET
M3D315
Rev. 01 -- 20 January 2003
Product data
1. Product profile
1.1 Description
N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOSTM technology. Product availability: PHK5NQ15T in SOT96-1 (SO8).
1.2 Features
s Low on-state resistance s Surface mount package.
1.3 Applications
s DC-DC primary side switching s General purpose switch.
1.4 Quick reference data
s VDS 150 V s Ptot 6.25 W s ID 5 A s RDSon 75 m
2. Pinning information
Table 1: Pin 1,2,3 4 5,6,7,8 Pinning - SOT96-1, simplified outline and symbol Description source (s) gate (g) drain (d)
g 1 Top view 4
MBK187
Simplified outline
8 5
Symbol
d
MBB076
s
SOT96-1
Philips Semiconductors
PHK5NQ15T
TrenchMOSTM standard level FET
3. Limiting values
Table 2: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM drain-source voltage (DC) drain-gate voltage (DC) gate-source voltage (DC) drain current (DC) peak drain current total power dissipation storage temperature junction temperature source (diode forward) current (DC) Tsp = 25 °C peak source (diode forward) current Tsp = 25 °C; pulsed; tp 10 µs Tsp = 25 °C; VGS = 10 V; Figure 2 and 3 Tsp = 100 °C; VGS = 10 V; Figure 2 Tsp = 25 °C; pulsed; tp 10 µs; Figure 3 Tsp = 25 °C; Figure 1 Conditions 25 °C Tj 150 °C 25 °C Tj 150 °C; RGS = 20 k Min -55 -55 Max 150 150 ±20 5 3.23 20 6.25 +150 +150 5 20 Unit V V V A A A W °C °C A A
Source-drain diode
9397 750 10774
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 01 -- 20 January 2003
2 of 12
Philips Semiconductors
PHK5NQ15T
TrenchMOSTM standard level FET
120 Pder (%) 80
03aa17
120 Ider (%) 80
03aa25
40
40
0 0 50 100 150 Tsp (°C) 200
0 0 50 100 150 200 Tsp (°C)
Pt o t P d e r = ---------------------- × 100 % P °
t o t ( 25 C )
VGS 10 V
ID I d e r = ------------------- × 100 % I °
D ( 25 C )
Fig 1. Normalized total power dissipation as a function of solder point temperature.
Fig 2. Normalized continuous drain current as a function of solder point temperature.
102 ID (A) 10 tp = 10 µs 1 ms 1 10 ms DC 100 ms 10-1 Limit RDSon = VDS/ID
003aaa242
10-2 10-1
1
10
102 VDS (V)
103
Tsp = 25 °C; IDM is single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 10774
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 01 -- 20 January 2003
3 of 12


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