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Part: PCK111
Category:
Logic
-> Clock Drivers/Distribution
Description: PCK111; Low Voltage 1:10 Differential Ecl/pecl/hstl Clock Driver;; Package: SOT358-1 (LQFP32)
Company: Philips Semiconductors
Datasheet: Download PCK111 datasheet File size : 6930 kB
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Datasheet text preview:
INTEGRATED CIRCUITS
PCK111 Low voltage 1:10 differential ECL/PECL/HSTL clock driver
Product data Supersedes data of 2002 Feb 15 2002 Dec 13
Philips Semiconductors
Philips Semiconductors
Product data
Low voltage 1:10 differential PECL clock driver
PCK111
FEATURES
· 85 ps part-to-part skew typical · 20 ps output-to-output skew typical · Differential design · VBB output · Low voltage VEE range of -2.25 V to -3.8 V for ECL · Low voltage VCC range of +2.375 V to +3.8 V for PECL · 75 k input pull-down resistors · ECL/PECL outputs · Form, fit, and function compatible with MC100EP111
DESCRIPTION
The PCK111 is a low skew 1-to-10 differential driver, designed with clock distribution in mind. It accepts two clock sources into an input multiplexer. The PECL input signals can be either differential or single-ended if the VBB output is used. The selected signal is fanned out to 10 identical differential outputs. The PCK111 is specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate-to-gate skew within a device, and empirical modeling is used to determine process control limits that ensure consistent tPD distributions from lot to lot. The net result is a dependable, guaranteed low skew device. To ensure that the tight skew specification is met, it is necessary that both sides of the differential output are terminated into 50 , even if only one side is being used. In most applications, all ten differential pairs will be used, and therefore terminated. In the case where fewer than ten pairs are used, it is necessary to terminate at least the output pairs on the same package side as the pair(s) being used on that side, in order to maintain minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20 ps) of the output(s) being used, which, while not being catastrophic to most designs, will mean a loss of skew margin. The PCK111 can be used for high performance clock distribution in +3.3 V or +2.5 V systems. Designers can take advantage of the PCK111's performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. The PCK111 may be driven single-endedly utilizing the VBB bias output with the CLK0 input. If a single-ended signal is to be used, the VBB pin should be connected to the CLK0 input and bypassed to ground via a 0.01 µF capacitor. The VBB output can only source/sink 0.2 mA, therefore, it should be used as a switching reference for the PCK111 only. Part-to-part skew specifications are not guaranteed when driving the PCK111 single-endedly.
PINNING Pin configuration
VCCO VCCO 25
Q0
Q0
Q1
Q1
Q2 27
32
31
30
29
28
VCC CLK_SEL CLK0 CLK0 V BB CLK1 CLK1 V EE
1 2 3 4
26
Q2
24 Q3 23 Q3 22 Q4 21 Q4
PCK111
5 6 7 8 20 Q5 19 Q5 18 Q6 17 Q6
Q9 10
Q8 12
Q8 13
Q7 14
Q7 15
VCCO 16
VCCO
Q9 11
9
SW00907
Figure 1. Pin configuration
Pin description
SYMBOL VCC CLK_SEL CLK0, CLK0 VBB CLK1, CLK1 VEE VCCO Q0-Q9 PIN 1 2 3, 4 5 6, 7 8 9, 16, 25, 32 31, 29, 27, 24, 22, 20, 18, 15, 13, 11 30, 28, 26, 23, 21, 19, 17, 14, 12, 10 DESCRIPTION Supply voltage Active CMOS clock select input Differential ECL/PECL/HSTL input pair Reference voltage output Differential ECL/PECL/HSTL input pair Ground Output drive power supply voltage Differential PECL outputs
Q0-Q9
Differential PECL outputs
ORDERING INFORMATION
Type number PCK111BD Package Name LQFP32 Description plastic low profile quad flat package; 32 leads; body 7 × 7 × 1.4 mm Version SOT358-1 Temperature range -40 to +85 °C
2002 Dec 13
2
Philips Semiconductors
Product data
Low voltage 1:10 differential PECL clock driver
PCK111
LOGIC SYMBOL
CLK0 CLK0 CLK1 CLK1 1 0 10 Q0:9 Q0:9
FUNCTION TABLE
CLK_SEL 0 1 Active input CLK0, CLK0 CLK1, CLK1
V BB CLK_SEL SW00908
Figure 2. Logic symbol
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. SYMBOL VCC ESDHBM ESDMM ESDCDM Supply voltage Electrostatic discharge (Human Body Model; 1.5 k, 100 pF) Electrostatic discharge (Machine Model; 0 k, 200 pF) Electrostatic discharge (Charge Device Model) PARAMETER LIMITS -0.5 to +4.6 >1.75 >200 >1000 UNIT V kV V V
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VIR VDIFF Tamb Supply voltage Receiver input voltage Input differential voltage1 V(CLKinN)- V(CLKin) Operating ambient temperature range in free air PARAMETER CONDITIONS MIN 2.25 VEE -- -40 MAX 3.8 VCC 1.00 +85 UNIT V V V °C
NOTE: 1. To idle an unused differential clock input, connect one input terminal (e.g. CLK1) to VBB and leave its complimentary input terminal (e.g. CLK1) open-circuit, in which case CLK1 will default low by its internal pull-down reistor. Inputs should not be shorted to ground or VCC.
2002 Dec 13
3
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