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Part: 10H20EV8-4A
Category:
Logic
Description: Ecl Programmable Array Logic
Company: Philips Semiconductors
Datasheet: Download 10H20EV8-4A datasheet File size : 172 kB
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Philips Semiconductors Programmable Logic Devices
Product specification
ECL programmable array logic
10H20EV8/10020EV8
DESCRIPTION
The 10H20EV8/10020EV8 is an ultra high-speed universal ECL PAL® device. Combining versatile output macrocells with a standard AND/OR single programmable array, this device is ideal in implementing a user 's custom logic. The use of Philips Semiconductors state-of-the-art bipolar oxide isolation process enables the 10H20EV8/10020EV8 to achieve optimum speed in any design. The SNAP design software package from Philips Semiconductors simplifies design entry based upon Boolean or state equations. The 10H20EV8/10020EV8 is a two-level logic element comprised of 11 fixed inputs, an input pin that can either be used as a clock or 12th input, 90 AND gates, and 8 Output Logic Macrocells. Each Output Macrocell can be individually configured as a dedicated input, dedicated output with polarity control, a bidirectional I/O, or as a registered output that has both output polarity control and feedback to the AND array. This gives the part the capability of having up to 20 inputs and eight outputs. The 10H20EV8/10020EV8 has a variable number of product terms that can be OR'd per output. Four of the outputs have 12 AND terms available and the other four have 8 terms per output. This allows the designer the extra flexibility to implement those functions that he couldn't in a standard PAL device. Asynchronous Preset and Reset product terms are also included for system design ease. Each output has a separate output enable product term. Another feature added for the system designer is a power-up Reset on all registered outputs.
The 10H20EV8/10020EV8 also features the ability to Preload the registers to any desired state during testing. The Preload is not affected by the pattern within the device, so can be performed at any step in the testing sequence. This permits full logical verification even after the device has been patterned.
PIN CONFIGURATIONS
F Package
I1 1 I2 2 CLK/I12 3 F1 4 24 VCC 23 I11 22 I10 21 F8 20 F7 19 VCO2 18 F6 17 F5 16 I9 15 I8 14 I7 13 I6
FEATURES
· Ultra high speed ECL device
tPD = 4.5ns (max) tIS = 2.6ns (max) tCKO = 2.3ns (max) fMAX = 208MHz
F2 5 VCO1 6 F3 7 F4 8 I3 9 I4 10 I5 11 VEE 12 F = Ceramic DIP (300mil-wide)
· Universal ECL Programmable Array Logic
8 user programmable output macrocells Up to 20 inputs and 8 outputs Individual user programmable output polarity
· Variable product term distribution allows
increased design capability
A Package
CLK/I12 I2 4 F1 5 F2 6 VCO1 7 NC 8 F3 9 F4 10 I3 11 12 I4 13 14 15 16 17 I7 18 I8 I5 VEE NC I6 3 I1 NC VCC I11 I10 2 1 28 27 26 25 F8 24 F7 23 VCO2 22 NC 21 F 6 20 F5 19 I9
· Asynchronous Preset and Reset capability · 10KH and 100K options · Power-up Reset and Preload function to
enhance state machine design and testing
· Design support provided via SNAP and
other CAD tools
· Security fuse for preventing design
duplication
· Available in 24-Pin 300mil-wide DIP and
28-Pin PLCC.
A = Plastic Leaded Chip Carrier
ORDERING INFORMATION
DESCRIPTION 24-Pin Ceramic Dual In-Line (300mil-wide) 28-Pin Plastic Leaded Chip Carrier ORDER CODE 10H20EV84F 10020EV84F 10H20EV84A 10020EV84A DRAWING NUMBER 0586B 0401F
®PAL is a registered trademark of Monolithic Memories, Inc., a wholly owned subsidiary of Advanced Micro Devices, Inc.
October 22, 1993
113
8531423 11164
Philips Semiconductors Programmable Logic Devices
Product specification
ECL programmable array logic
10H20EV8/10020EV8
LOGIC DIAGRAM
3 0 D 0 OUTPUT LOGIC MACRO CELL 4 4 8 12 INPUT LINES 16 20 24 28 32 36
7
D 0 OUTPUT LOGIC MACRO CELL 21
7 1 D 0
11 2 D 0
OUTPUT LOGIC MACRO CELL
5
11 9 D 0
OUTPUT LOGIC MACRO CELL
20
11 10 D 0
OUTPUT LOGIC MACRO CELL
7
11 11 D 0
OUTPUT LOGIC MACRO CELL
18
7
OUTPUT LOGIC MACRO CELL
8
13 D 0 OUTPUT LOGIC MACRO CELL 17
7 14 15 16
23 22 ASYNCHRONOUS RESET ASYNCHRONOUS PRESET
NOTES: 1. All unprogrammed or virgin "AND" gate locations are pulled to logic "0" 2. Programmable connections 3. Pinout for F Package
October 22, 1993
114
Philips Semiconductors Programmable Logic Devices
Product specification
ECL programmable array logic
10H20EV8/10020EV8
FUNCTIONAL DIAGRAM
CLK/I I
1
11
PROGRAMMABLE AND ARRAY (90 × 40)
12 12 8 8 8 8 12 12
RESET
OUTPUT LOGIC MACROCELL
OUTPUT LOGIC MACROCELL
OUTPUT LOGIC MACROCELL
OUTPUT LOGIC MACROCELL
OUTPUT LOGIC MACROCELL
OUTPUT LOGIC MACROCELL
OUTPUT LOGIC MACROCELL
OUTPUT LOGIC MACROCELL
PRESET
F
F
F
F
F
F
F
F
FUNCTIONAL DESCRIPTION
The 10H20EV8/10020EV8 is an ultra high-speed universal ECL PAL-type device. Combining versatile Output Macrocells with a standard AND/OR single programmable array, this device is ideal in implementing a user 's custom logic.
As can be seen in the Logic Diagram, the device is a two-level logic element with a programmable AND array. The 20EV8 can have up to 20 inputs and 8 outputs. Each output has a versatile Macrocell whereby the output can either be configured as a dedicated input, a dedicated combinatorial output with polarity control, a bidirectional I/O, or as a registered output that has both output polarity control and feedback into the AND array.
The device also features 90 product terms. Two of the product terms can be used for a global asynchronous preset and/or reset. Eight of the product terms can be used for individual output enable control of each Macrocell. The other 80 product terms are distributed among the outputs. Four of the outputs have eight product terms, while the other four have 12. This arrangement allows the utmost in flexibility when implementing user patterns.
Output Logic Macrocell
The 10H20EV8/10020EV8 incorporates an extremely versatile Output Logic Macrocell that allows the user complete flexibility when configuring outputs. As seen in Figure 1, the 10H20EV8/ 10020EV8 Output Logic Macrocell consists of an edge-triggered D-type flip-flop, an output select MUX, and a feedback select MUX. Fuses S0 and S1 allow the user to select between the various cells. S1 controls whether the output will be either registered with internal feedback or combinatorial I/O. S0 controls the polarity of the output (ActiveHIGH or Active-LOW). This allows the user to achieve the following configurations: Registered Active-HIGH output, Registered Active-LOW output, Combinatorial ActiveHIGH output, and Combinatorial Active-LOW output. With the output enable product term, this list can be extended by adding the configurations of a Combinatorial I/O with Polarity or another input.
Fn AP D Q OUTPUT SELECT MUX S1 S0
CLK AR
Q
V CC
FEEDBACK MUX V CC S1
Figure 1. Output Logic Macrocell
October 22, 1993
115
Philips Semiconductors Programmable Logic Devices
Product specification
ECL programmable array logic
10H20EV8/10020EV8
ABSOLUTE MAXIMUM RATINGS1
SYMBOL VEE VIN IO TS TJ Supply voltage Input voltage (VIN should never be more negative than VEE) Output source current Operating Temperature range Storage Temperature range Ceramic Package Plastic Package PARAMETER RATING 8.0 0 to VEE 50 55 to +150 +165 +150 UNIT V V mA °C °C °C
NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.
DC OPERATING CONDITIONS 10H20EV8
TEST SYMBOL VCC, VCO1, VCO2 VEE Circuit ground Supply voltage (negative) Tamb = 0°C VIH High level input voltage Tamb = +25°C Tamb = +75°C Tamb = 0°C VIL Low level input voltage Tamb = +25°C Tamb = +75°C Tamb Operating ambient temperature range 1170 1130 1070 1950 1950 1980 0 +25 PARAMETER CONDITIONS MIN 0 LIMITS NOM 0 5.2 840 810 735 1480 1480 1450 +75 MAX 0 UNIT V V mV mV mV mV mV mV °C
NOTE: When operating at other than the specified VEE voltage (5.2V), the DC and AC Electrical Characteristics will vary slightly from specified values.
DC OPERATING CONDITIONS 10020EV8
TEST SYMBOL VCC, VCO1, VCO2 VEE VEE Circuit ground Supply voltage Supply voltage when opetating with the 10K or 10KH ECL family VEE = 4.2V VIH High level input voltage VEE = 4.5V VEE = 4.8V VEE = 4.2V VIL Low level input voltage VEE = 4.5V VEE = 4.8V Tamb Operating ambient temperature range 0 +25 1810 PARAMETER CONDITIONS MIN 0 4.8 5.7 1150 1165 1165 1475 1475 1490 +85 mV mV mV °C 880 mV LIMITS NOM 0 4.5 MAX 0 4.2 UNIT V V V
NOTE: When operating at other than the specified VEE voltages (4.2V, 4.5V, 4.8V), the DC and AC Electrical Characteristics will vary slightly from their specified values.
October 22, 1993
116
Philips Semiconductors Programmable Logic Devices
Product specification
ECL programmable array logic
10H20EV8/10020EV8
D AP
D AP
D
Q
D
Q
CK
Q AR
CK
Q AR
Registered Active-HIGH
Registered Active-LOW
D
D
Combinatorial Active-HIGH Figure 2.
Combinatorial Active-LOW Output Macro Cell Configurations Active-HIGH and Active-LOW, a Preset signal will force the Active-HIGH outputs HIGH while the Active-LOW outputs would go LOW, even though the Q output of all flip-flops would go HIGH. A Reset signal would force the opposite conditions.
OUTPUT MACRO CELL CONFIGURATION
Shown in Figure 2 are the four possible configurations of the output macrocell using fuses S0 and S1. As seen, the output can either be registered Active-HIGH/LOW with feedback or combinatorial Active-HIGH/LOW with feedback. If the registered mode is chosen, the feedback from the Q output to the AND array enables one to make state machines or shift registers without having to tie the output to one of the inputs. If a combinatorial output is chosen, the feedback gate is enabled from the pin and allows one to create permanent outputs, permanent inputs, or I/O pins through the use of the output enable (D) product term.
controlled by a programmed pattern. A HIGH on the D term enables the output, while a LOW performs the disable function. Output enable control can be achieved by programming a pattern on the D term. The output enable control can also be used to expand a designer's possibilities once a combinatorial output has been chosen. If the D term is always HIGH, the pin becomes a permanent Active-HIGH/LOW output. If the D term is always LOW (all fuses left intact), the pin now becomes an extra input.
PRELOAD
To simplify testing, the 10H20EV8/10020EV8 has also included PRELOAD circuitry. This allows a user to load any particular data desired into the registers regardless of the programmed pattern. This means that the PRELOAD can be done on a blank part and after that same part has been programmed to facilitate any post-fuse testing desired. It can also be used by a designer to help debug a circuit. This could be important if a state machine was implemented in the 10H20EV8/ 10020EV8. The PRELOAD would allow the entry of any state in the sequence desired and start clocking from that particular point. Any or all transitions could be verified.
PRESET AND RESET
The 10H20EV8/10020EV8 also includes a separate product term for asynchronous Preset and asynchronous Reset. These lines are common for all registers and are asserted when the specific product term goes HIGH. Being asynchronous, they are independent of the clock. It should be noted that the actual state of the output is dependent on how the polarity of the particular output has been chosen. If the outputs are a mix of
OUTPUT ENABLE
Each output on the 10H20EV8/10020EV8 has its own individual product term for output enable. The use of the D product term (direction control) allows the user three possible configurations of the outputs. They are: always enabled, always disabled, and
October 22, 1993
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