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Part: PI74LVTCH16374AE
Category:
Logic
Description: 3.3V 16-Bit Edge Triggered D-type Flip-flop W/3-State Outputs
Company: Pericom Semiconductor Corporation
Datasheet: Download PI74LVTCH16374AE datasheet File size : 31 kB
Request For quote: Find where to buy PI74LVTCH16374AE
Datasheet text preview:
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LVTCH16374
3.3V 16-Bit Edge Triggered D-Type Flip-Flop with 3-State Outputs
Product Features
· Advanced low power CMOS design for 2.7V to 3.6V Vcc operation · Supports 5V input/output tolerance in mixed signal mode operation · Function compatible with LVT family of products · Balanced ±24mA output drive · Typical VOLP (Output Ground Bounce) <0.8V at VCC=3.3V, TA=25°C · Ioff and Power Up/Down 3-State support live insertion · Bus Hold on data inputs eliminates the need for external pull-up/down resistors · Latch-up performance exceeds 200mA Per JESD78 · ESD protection exceeds JESD 22 - 2000V Human-Body Model (A114-B) - 200V Machine Model (A115-A) · Packages(Pb-free available): - 48-pin 240-mil wide plastic TSSOP (A48) - 48-pin 300-mil wide plastic SSOP (V48) · Industrial Temperature: -40°C to +85°C
Product Description
Pericom Semiconductor's PI74LVTC series of logic circuits are produced using Pericom's advanced CMOS technology, achieving industry leading speed. The PI74LVTCH16374 is a 16-bit edge-triggered D-type Flip-Flop designed for low-voltage 2.7V to 3.6V VCC operation, with the capability of interfacing to the 5V system environment. This D-type Flip-Flop is particularly suitable for implementing buffers registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the Clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data D inputs. A buffered output enable (OE) can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high impedance state. The PI74LVTCH16374 has "Bus Hold" which retains the data input's last valid logic state whenever the data input goes to highimpedance, preventing "floating" inputs and eliminating the need for pull-up/down resistors. When Vcc is between 0 to 1.5V during power up or power down, the outputs of the device are in the high-impedance state. To ensure the high-impedance state above 1.5V, OE should be tied to Vcc through a pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the driver. The device fully supports live-insertion with its Ioff and power-up/ down 3-state. The Ioff circuitry disables the outputs when the power is off, preventing the backflow of damaging current through the device. Power-up/down 3-state places the outputs in the highimpedance state during power up or power down, preventing driver conflict.
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Logic Block Diagram
1OE
1
1CLK
48
C1
2
1Q1
1D1
47
1D
To Seven Other Channels
24
2OE 2CLK
25
C1 2Q1 2D1
36
1D
To Seven Other Channels
1
PS 8654A
05/19/03
Truth Table(4)
Inputs xOE L L L H xCLK H or L X xDx H L X X Outputs xQx H L Q0 Z
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LVTCH16374 3.3V 16-Bit Edge Triggered D-Type Flip-Flop with 3-State Output
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply voltage range, VCC ...... 0.5V to +6.5V Input voltage range, VI(1) ......... 0.5V to +6.5V Voltage range applied to any output in the high-impedance or power-off state, VO(1) ........ 0.5V to +6.5V Voltage range applied to any output in the active state, VO(1) ,(2) .......... 0.5V to VCC +0.5V Input clamp current, IIK (VI <0) .... 50mA Output clamp current, IOK (VO <0) ....... 50mA Continous Output Current IO ...... ±50mA Continous Current through each VCC or GND pin ..... ±100mA Package thermal impedance, JA(3): package A ......... 104°C/W package V .. 94°C/W Storage Temperature range, Tstg ............ 65°C to 150°C
Notes: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. Input negative-voltage and output voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 6.5V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51.
Product Pin Description
Pin Name xOE xCLK xDx xQx GND VC C De s cription Output Enable Input (Active LOW) Clock Input (Active HIGH) Data Inputs 3- State Outputs Ground Power
Product Pin Configuration
1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE 1CLK 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2D7 2D8 2CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40
48-Pin A, V
39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
Notes: 4. H = High Signal Level L = Low Signal Level Q 0 = Previous xQx After the last LOW-to-HIGH Transition of CLK Input. X = Don't Care or Irrelevant Z = High Impedance
2
PS 8654A
05/19/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LVTCH16374 3.3V 16-Bit Edge Triggered D-Type Flip-Flop with 3-State Output
Recommended Operating Conditions(5)
M in. VCC VIH VIL VI VO Supply Voltage High- level Input Voltage Low- level Input Voltage Input Voltage Output Voltage High or Low State 3- State IOH High- level output current IOL Low- level output current t/v Input transition rise or fall rate t/VCC Power- up ramp rate TA Operating free- air temperature 150 40 85 VCC = 2.7V VCC = 3.0V to 3.6V VCC = 2.7V VCC = 3.0V to 3.6V Operating VCC = 2.7V to 3.6V VCC = 2.7V to 3.6V 0 0 0 2.7 2.0 0.8 5.5 VCC 5.5 12 24 12 24 10 ns/V µs/V °C mA M a x. 3.6 Units V
Notes: 5.All unused inputs must be held at VCC or GND to ensure proper device operation.
3
PS 8654A
05/19/03
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