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Part: PI74LVTC244
Category:
Logic
Description: 3.3V 8-Bit Buffer/line Driver W/3-State Outputs
Company: Pericom Semiconductor Corporation
Datasheet: Download PI74LVTC244 datasheet File size : 31 kB
Request For quote: Find where to buy PI74LVTC244
Datasheet text preview:
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PI74LVTC244
3.3V 8-Bit Buffers/Line Drivers with 3-State Outputs
Product Features
· Advanced low power CMOS design for 2.7V to 3.6V VCC operation · Supports 5V input/output tolerance in mixed signal mode operation · Function compatible with LVT family of products · Balanced ±24mA output drive · Typical VOLP (Output Ground Bounce) <0.8V at VCC=3.3V, TA=25°C · Ioff and Power Up/Down 3-State support live insertion · Latch-up performance exceeds 200mA Per JESD78 · ESD protection exceeds JESD 22 - 2000V Human-Body Model (A114-B) - 200V Machine Model (A115-A) · Packages (Pb-free available): - 20-pin 209-mil wide plastic SSOP (H20) - 20-pin 173-mil wide plastic TSSOP (L20) - 20-pin 300-mil wide plastic SOIC (S20)
Product Description
Pericom Semiconductor's PI74LVTC series of logic circuits are produced using the Company's advanced CMOS technology, achieving industry leading speed. The PI74LVTC244 is a non-inverting 8-bit buffer and line driver designed for low-voltage 2.7V to 3.6V VCC operation, with the capability of interfacing to the 5V system environment. With its balanced drive characteristics, this high-speed, low power device provides low ground bounce and transmission line impedance matching. This makes it ideal for driving on board buses and transmission lines. The device can be used as two 4-bit buffers with separate output enable (OE) inputs. When VCC is between 0 to 1.5V during power up or power down, the outputs of the device are in the high-impedance state. To ensure the high-impedance state above 1.5V, OE should be tied to Vcc through a pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the driver. The device fully supports live-insertion with its Ioff and power-up/ down 3-state. The Ioff circuitry disables the outputs when the power is off, preventing the backflow of damaging current through the device. Power-up/down 3-state places the outputs in the high-impedance state during power up or power down, preventing driver conflict.
Logic Block Diagram
1OE 1A1 1 2 18
2OE 1Y1 2A1
19 11 9
2Y1
1A2
4
16
1Y2
2A2
13
7
2Y2
1A3
6
14
1Y3
2A3
15
5
2Y3
1A4
8
12
1Y4
2A4
17
3
2Y4
1
PS8691
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Truth Table(4)
Inputs xOE L L H
Notes: 4. H = High Signal Level L = Low Signal Level X = Don't Care or Irrelevant Z = High Impedance
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LVTC244 3.3V 8-Bit Buffers/Line Drivers with 3-State Outputs
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply voltage range, VCC ...... 0.5V to +6.5V Input voltage range, VI(1) ........ 0.5V to +6.5V Voltage range applied to any output in the high-impedance or power-off state, VO(1) ....... 0.5V to +6.5V Voltage range applied to any output in the active state, VO(1), (2) ........ 0.5V to VCC +0.5V Input clamp current, IIK (VI <0) .... 50mA Output clamp current, IOK (VO <0) ....... 50mA Continous Output Current IO ...... ±50mA Continous Current through each VCC or GND pin ...... ±100mA Package thermal impedance, JA(3): package H .. 81°C/W package L ... 84°C/W package S ... 84°C/W Storage Temperature range, Tstg ............ 65°C to 150°C
Notes: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. Input negative-voltage and output voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 6.5V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51.
Product Pin Description
Pin Name xOE xAx xYx GND VC C Inputs 3- State Outputs Ground Power De s cription 3- State Output Enable Inputs (Active LOW)
Product Pin Configuration
1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC 2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1
20-Pin H, L, S
Outputs xAx H L X xYx H L Z
2
PS8691
07/01/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LVTC244 3.3V 8-Bit Buffers/Line Drivers with 3-State Outputs
Recommended Operating Conditions(5)
M in. VC C VIH VIL VI VO Supply Voltage High- level Input Voltage Low- level Input Voltage Input Voltage Output Voltage High or Low State 3- State VC C = 2.7V VC C = 3.0V to 3.6V VC C = 2.7V VC C = 3.0V to 3.6V Operating VC C = 2.7V to 3.6V VC C = 2.7V to 3.6V 0 0 0 2.7 2.0 0.8 5.5 VC C 5.5 12 24 12 24 10 150 40 85 ns/V µs/V °C mA V M a x. 3.6 Units
IO H High- level output current IO L Low- level output current t/V Input transition rise or fall rate t/VC C Power- up ramp rate TA Operating free- air temperature
Notes: 5. All unused inputs must be held at VCC or GND to ensure proper device operation.
3
PS8691
07/01/03
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