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Part: PI74ALVCH16524

Category:
 Logic
   -> Bus Interface
             -> Bus Oriented Circuits

Description: 18-Bit Registered Bus Exchanger

Company: Pericom Semiconductor Corporation

Datasheet: Download PI74ALVCH16524 datasheet     File size : 313 kB

Request For quote: Find where to buy PI74ALVCH16524



Datasheet text preview:
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH16524
18-Bit Registered Bus Transceiver With 3-State Outputs
Product Features
· PI74ALVCH16524 is designed for low voltage operation · VCC = 2.3V to 3.6V · Typical VOLP (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25°C · Typical VOHV (Output VOH Undershoot) < 2.0V at VCC = 3.3V, TA = 25°C · Bus Hold retains last active bus state during 3-State eliminating the need for external pullup resistors · Industrial operation at 40°C to +85°C · Packages available: 56-pin 240 mil wide plastic TSSOP (A) 56-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductors PI74ALVCH series of logic circuits are produced using the Companys advanced 0.5 micron CMOS technology, achieving industry leading speed. The PI74ALVCH16524 data flow in each direction is controlled b y output-enable (OEAB and OEBA) and clock-enable (CLKENBA) inputs. For the A-to-B data flow, the data flows through a single buffer. The B-to-A data can flow through a fourstage pipeline register path, or through a single register path, depending on the state of the select (SEL) input. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input, provided that the appropriate CLKENBA input is low. The B-to-A data transfer is synchronized with CLK. To ensure the high-impedance state during power up or power down, OE should be tied to Vcc through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The PI74ALVCH16524 has Bus Hold which retains the data inputs last state whenever the data input goes to high-impedance preventing floating inputs and eliminating the need for pullup/ down resistors.
Logic Block Diagram
CLK CLKENBA OEAB OEBA SEL 30 28 2 27 55 1 of 18 Channels
CE A1
G1 1 1
CE C1 1D
CE C1 1D
CE C1 1D
3
C1 1D
54
B1
To 17 Other Channels
1
PS8447A
11/06/00
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH16524 18-Bit Registered Bus Transceiver with 3-State Outputs
Product Pin Description
Pin Name CLKEN SEL CLK Ax Bx GND VCC Description Clock Enable Input (Active LOW) Select (Active LOW) Clock Input (Active HIGH) Data I/O Data I/O Ground Power
Truth Table(1) B to A Storage (OEBA = L)
Inputs CLKENBA H L L L L CLK X SEL X H H L L B X L H L H Outputs A A0 L H L§ H§
Product Pin Configuration
GND OEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA CLKENBA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
GND SEL B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 CLK GND
Note: 1. H = High Signal Level L = Low Signal Level Z = High Impedance = LOW-to-HIGH Transition Output level before the indicated steady-state input conditions were established. § Four positive CLK edges are needed to propagate data from B to A when SEL is low.
56-Pin 46 A,V
2
PS8447A
11/06/00
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH16524 18-Bit Registered Bus Transceiver with 3-State Outputs
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ........ 65°C to +150°C Supply Voltage Range, VCC .... 0.5V to 4.6V Input Voltage Range,VI: Except I/O ports(1) .......... 0.5V to 4.6V I/O ports(1,2) .......... 0.5V to VCC + 0.5V Output Voltage Range, VO(1,2) .......... 0.5V to VCC + 0.5V Input Clamp current, IIK (VI < 0) ...... 50mA Output Clamp current, IOK (VO < 0) .......... 50mA Continous Output Current, IO ......... ±50mA Continous Current through each VCC or GND ...... ±100mA Maximum Power Dissipation: A package ....... 1W V package .... 1.4W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Notes: 1. The input and output negative-voltage ratings maybe exceeded if the input and outputclamp-current ratings are observed. 2. This value is limited to 4.6V maximum.
Recommended Operating Conditions(1)
Parame te rs VCC VIH VIL VIN VOU T IOH De s cription Supply Voltage Input HIGH Voltage VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V 0 0 VCC = 2.3V High- level Output Current VCC = 2.7V VCC = 3.0V VCC = 2.3V IOL TA t/v(2) Low- level Output Current VCC = 2.7V VCC = 3.0V Operating Free- Air Temperature Input Transition Rise or Fall 40 Te s t Conditions M in. 2.3 1.7 2.0 0.7 0.8 VCC VCC 12 12 24 12 12 24 85 10 °C ns/V mA V Typ. M ax. 3.6 Units
Input LOW Voltage Input Voltage Output Voltage
Note: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. 2. See test circuit and waveforms.
3
PS8447A
11/06/00


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