|
|
Part: PI74ALVCH16501
Category:
Logic
-> Bus Interface
-> Bus Oriented Circuits
Description: 18-Bit Universal Bus Transceiver
Company: Pericom Semiconductor Corporation
Datasheet: Download PI74ALVCH16501 datasheet File size : 313 kB
Request For quote: Find where to buy PI74ALVCH16501
Datasheet text preview:
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH16501
18-Bit Universal Bus Transceiver With 3-State Outputs
Product Features
· · · · · · · · PI74ALVCH16501 is designed for low voltage operation VCC = 2.3V to 3.6V Hysteresis on all inputs Typical VOLP (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25°C Typical VOHV (Output VOH Undershoot) < 2.0V at VCC = 3.3V, TA = 25°C Bus Hold retains last active bus state during 3-STATE eliminating the need for external pullup resistors Industrial operation at 40°C to +85°C Packages available: 48-pin 240 mil wide plastic TSSOP (A) 48-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor's PI74ALVCH series of logic circuits are produced in the Company's advanced 0.5 micron CMOS technology, achieving industry leading speed. The 18-bit PI74ALVCH16501 univeral bus transceiver is designed for 2.3V to 3.6V VCC operation. Data flow in each direction is controlled by Output Enable (OEAB and OEBA), Latched Enable (LEAB and LEBA), and CLOCK (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is LOW, the A-bus is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the highimpedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The Output Enables are complementary (OEAB is active HIGH and OEBA is active LOW). To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a pull-up resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Logic Block Diagram
1
PS8133A
01/31/00
Product Pin Description
Pin Name OE LE CLK Ax Bx GND VCC Description Output Enable Input (Active HIGH) Latch Enable (Active HIGH) Clock Input (Active HIGH) Data I/O Data I/O Ground Power
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER
Truth Table(1)
Inputs Output B OEAB L H H H H H LEAB X H H L L L L CLKAB X X X H L A X L H L H X X Z L H L H B0 B0§
Product Pin Configuration
H
OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50
GND CLKAB B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 CLKBA GND
56-PIN 49 V-56 48 A-56
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
Notes: 1. H = High Signal Level L = Low Signal Level Z = High Impedance = LOW-to-HIGH Transition A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, CLKBA. Output level before the indicated steady-state input conditions were established, provided that CLKAB is HIGH before LEAB goes LOW. § Output level before the indicated steady-state input conditions were established.
2
PS8133A
01/31/00
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .. 65°C to +150°C Ambient Temperature with Power Applied ...... 40°C to +85°C Input Voltage Range, VIN ...... 0.5V to VCC +0.5V Output Voltage Range, VOUT ..... 0.5V to VCC +0.5V DC Input Voltage ........... 0.5V to +5.0V DC Output Current .......... 100 mA Power Dissipation .......... 1.0W
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended Operating Conditions(1)
Parame te rs VCC VIH De s cription Supply Voltage Input HIGH Voltage VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V Input LOW Voltage Input Voltage Output Voltage VCC = 2.3V IOH High- level Output Current VCC = 2.7V VCC = 3.0V VCC = 2.3V IOL Low- level Output Current VCC = 2.7V VCC = 3.0V TA Operating Free- Air Temperature - 40 VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V 0 0 Te s t Conditions M in. 2.3 1.7 2.0 0.7 0.8 VCC VCC - 12 - 12 - 24 mA 12 12 24 85 °C V Typ. M ax. 3.6 Units
VIL VIN VOUT
Note: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
3
PS8133A
01/31/00
Others parts begin by pi
PI-1 PI-2 PI-3 PI-4 PI-5 PI-6 PI-7 PI-8 PI-9 PI-10 PI-11 PI-12 PI-13 PI-14 PI-15 PI-16 PI-17 PI-18 PI-19 PI-20 PI-21 PI-22 PI-23 PI-24 PI-25 PI-26 PI-27 PI-28 PI-29 PI-30 PI-31 PI-32 PI-33 PI-34 PI-35 PI-36 PI-37 PI-38 PI-39 PI-40 PI-41 PI-42 PI-43 PI-44 PI-45 PI-46 PI-47 PI-48 PI-49 PI-50 PI-51 PI-52 PI-53 PI-54 PI-55 PI-56 PI-57 PI-58 PI-59 PI-60 PI-61 PI-62 PI-63 PI-64 PI-65 PI-66
|
|
|
