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Part: PI74ALVCH16271V
Category: Logic -> Bus Interface -> Bus Oriented Circuits
Description: 12/24-Bit Multiplexed Bus Exchanger
Company: Pericom Semiconductor Corporation
Datasheet: Download PI74ALVCH16271V datasheet File size : 313 kB
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Datasheet text preview:
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH16271
12-Bit To 24-Bit Multiplexed Bus Exchanger with 3-State Outputs
Product Features
· PI74ALVCH16271 is designed for low voltage operation, VCC = 2.3V to 3.6V · Hysteresis on all inputs · Typical VOLP (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25°C · Typical VOHV (Output VOH Undershoot) < 2.0V at VCC = 3.3V, TA = 25°C · Bus Hold retains last active bus state during 3-State, eliminating the need for external pullup resistors · Industrial operation at 40°C to +85°C · Packages available: 56-pin 240 mil wide plastic TSSOP (A56) 56-pin 300 mil wide plastic SSOP (V56)
Product Description
Pericom Semiconductor's PI74AVC series of logic circuits are produced using the Company's advanced 0.35 micron CMOS technology, achieving industry leading speed. This 12-bit to 24-bit multiplexed bus exchanger is designed for 2.3V to 3.6V VCC operation. The PI74ALVCH16271is intended for applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. This device is particularly suitable as an i n t e r f a c e between conventional DRAMs and high-speed microprocessors Data is stored in the internal A-to-B registers on the low-to-high transition of the clock (CLK) input, provided clock-enable (CLKENA) inputs are low. Proper control of these inputs allows two sequential 12-bit words to be presented as a 24-bit word on the B port. To maximize memory access throughput, transparent latches in the B-to-A path allow asynchronous operation. These latches transfer data when the latch-enable (LE) inputs are low. The select (SEL) line selects 1B or 2B data for the A outputs. Data flow is controlled by the active-low output enables (OEA, OEB). To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor, the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Logic Block Diagram
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Product Pin Description
Pin Name OE CLK SEL CLKEN A,1B,2B GND V CC Description Output Enable Input (Active LOW) Clock Select (Active Low) Clock Enable (Active Low) 3-State Outputs Ground Power
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PI74ALVCH16271 12-Bit To 24-Bit Multiplexed Bus Exchanger with 3-State Outputs Product Pin Configuration
OEA LE1B 2B3 GND 2B2 2B1 VCC A1 A2 A3 GND A4
1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48
OEB CLKENA2 2B4 GND 2B5 2B6 VCC 2B7 2B8 2B9 GND 2B10 2B11 2B12 1B12 1B11 1B10 GND 1B9 1B8 1B7 VCC 1B6 1B5 GND 1B4 CLKENA1 CLK
Truth Tables(1)
Output Enable
INPUTS OEA H H L L OEB H L H L A Z Z Active Active OUTPUTS 1B,2B Z Active Z Active
47 11 56-PIN 46
A5 A6 A7 A8 A9 GND A10 A11 A12 VCC
A56 V56
45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
A to B STORAGE (OEB = L)
INPUTS CLKENA1 H L L X X CLKENA2 H X X L L CLK X A X L H L H OUTPUTS 1B 1B0(2) L H X AO 2B 2B0(2) X X L H
1B1 1B2 GND 1B3 LE2B SEL
B to A STORAGE (OEA = L)
INPUTS LE H H L L L L SEL X X H H L L 1B X X L H X X 2B X X X X L H Outputs A AO(2) AO(2) L H L H
Notes: 1. H = High Signal Level, L = Low Signal Level X = Irrelevant, Z = High Impedance = Transition, Low to High 2. Output level before the indicated steady state input conditions were established.
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH16271 12-Bit To 24-Bit Multiplexed Bus Exchanger with 3-State Outputs
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ........ 65°C to +150°C Supply Voltage Range, VCC .......... 0.5V to 4.6V Input Voltage Range,VI : Except I/O ports (See Note 1): ....... 0.5V to 4.6V I/O ports (See Notes 1 and 2) ...... 0.5V to VCC + 0.5V Output Voltage Range, VO (See Notes 1and 2) .. 0.5V to VCC + 0.5V Input Clamp current, IIK (VI VCC) .......... ±50mA Continous Output Current, IO (VO = 0 to VCC) ...... ±50mA Continous Current through each VCC or GND ...... ±100mA Maximum Power Dissipation: A package .......... 1W V package ....... 1.4W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Notes: 1. The input and output negative-voltage ratings maybe exceeded if the input and outputclamp-current ratings are observed. 2. This value is limited to 4.6V maximum.
DC Electrical Characteristics (Over the Operating Range, TA = 40°C to +85°C, VCC = 3.3V ± 10%)
Parame te rs VCC VIH VIL VIN VOUT IOH De s cription Supply Voltage Input HIGH Voltage VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V 0 0 VCC = 2.3V HIGH- level Output Current VCC = 2.7V VCC = 3.0V VCC = 2.3V IOL LOW- level Output Current VCC = 2.7V VCC = 3.0V Te s t Conditions (3) M in. 2.3 1.7 2.0 0.7 0.8 VCC VCC - 12 - 12 - 24 12 12 24 mA V Typ. M ax. 3.6 Units
Input LOW Voltage Input Voltage Output Voltage
Note: 3. Unused control inputs must be held HIGH or LOW to prevent them from floating.
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