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Part: PI6C41202
Category:
Timing Circuits
-> Clock & Timing
Description: 2 Outputs, Lvttl/lvcmos to Lvpecl Clock Converter, Selectable Inputs
Company: Pericom Semiconductor Corporation
Datasheet: Download PI6C41202 datasheet File size : 292 kB
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Datasheet text preview:
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C41202 PI6C41204 PI6C41204A
LVCMOS to LVPECL Driver
Features
· Up to Four LVPECL outputs · · · · · · · Selectable CLK0 or CLK1 inputs LVCMOS or LVTTL input level 30ps max output skew 150ps max part-to-part skew 1.9ns max propagation delay 266 MHz output frequency 14-pin, and 20-pin TSSOP packaging
Description
PI6C4120x is a high-performance LVCMOS or LVTTL to LVPECL clock buffer. The PI6C41204 is a 4 output version with 2 selectable inputs, pin compatible with ICS8535-01. PI6C41204A is the enhanced version with extra power and ground pins to minimize noise and jitter. The PI6C41202 is similar to the PI6C41204 except is has two outputs.
Block Diagram PI6C41204/A
CLK_EN CLK0 CLK1 0 1 D Q LE Q0 nQ0 Q1 nQ1 CLK_SEL Q2 nQ2 Q1 nQ3
Pin Configuration PI6C41204/A
Vee CLK_EN CK_SEL CLK0 nc/Vee CLK1 nc/Vee nc/Vee nc/Vcc Vcc
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
20-Pin
Q0 nQ0 Vcc Q1 nQ1 Q2 nQ2 Vcc Q3 nQ3
Block Diagram PI6C41202
CLK_EN CLK0 CLK1 0 1 D Q LE Q0 nQ0 Q1 nQ1 CLK_SEL
Pin Configuration PI6C41202
Vee CLK_EN CK_SEL CLK0 Vee CLK1 Vcc
1 2 3 4 5 6 7 14 13
14-Pin 12
11 10 9 8
Vcc Q0 nQ0 nc Q1 nQ1 Vcc
1
PS8626A
05/01/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C4120x LVCMOS to LVPECL Driver
Table 1a. Pin Description for PI6C41204
N umbe r
1 2
N a me
Vee C LK _EN P o wer Inp ut
Type
Gro und . P ullup
D e s criptio n
S ynchro nizing clo ck enab le. When HIGH, clo ck o utp uts fo llo w clo ck inp ut. When LO W, Q are lo w, nQ are high. LVC MO S o r LVTTL inp ut level. C lo ck select inp ut: LO W = C LK 0 , HIGH = C LK 1 LVC MO S o r LVTTL inp ut level. LVC MO S o r LVTTL clo ck inp ut. LVC MO S o r LVTTL inp ut level. N o C o nnect 3 . 3 V sup p ly LVP EC L o utp ut p air. LVP EC L o utp ut p air. LVP EC L o utp ut p air. LVP EC L o utp ut p air.
3 4 6 5, 7, 8, 9 10, 13, 18 11, 12 14, 15 16, 17 19, 20
C LK _S EL C LK 0 C LK 1 NC Vcc nQ 3 , Q 3 nQ 2 , Q 2 nQ 1, Q 1 nQ 0 , Q 0
Inp ut Inp ut Inp ut Unused P o wer O utp ut O utp ut O utp ut O utp ut
P ulld o wn P ulld o wn P ulld o wn
Table 1b. Pin Description for PI6C41204A
N umbe r
1, 5, 7, 8 2
N a me
Vee C LK _EN P o wer Inp ut
Type
Gro und . P ullup
D e s criptio n
S ynchro nizing clo ck enab le. When HIGH, clo ck o utp uts fo llo w clo ck inp ut. When LO W, Q are lo w, nQ are high. LVC MO S o r LVTTL inp ut level. C lo ck select inp ut: LO W = C LK 0 , HIGH = C LK 1 LVC MO S o r LVTTL inp ut level LVC MO S o r LVTTL clo ck inp ut. LVC MO S o r LVTTL inp ut level. 3 . 3 V sup p ly LVP EC L o utp ut p air. LVP EC L o utp ut p air. LVP EC L o utp ut p air. LVP EC L o utp ut p air.
3 4 6 9, 10, 13, 18 11, 12 14, 15 16, 17 19, 20
C LK _S EL C LK 0 C LK 1 Vcc nQ 3 , Q 3 nQ 2 , Q 2 nQ 1, Q 1 nQ 0 , Q 0
Inp ut Inp ut Inp ut P o wer O utp ut O utp ut O utp ut O utp ut
P ulld o wn P ulld o wn P ulld o wn
2
PS8626A
05/01/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C4120x LVCMOS to LVPECL Driver
Table 1c. Pin Description for PI6C41202
Numbe r 1, 5 2 Name Vee CLK_EN Power Input Pullup Type Ground. Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q are low, nQ are high. LVCMOS or LVTTL input level. Clock select input: LOW = CLK0, HIGH = CLK1 LVCMOS or LVTTL input level. LVCMOS or LVTTL clock input. LVCMOS or LVTTL input level. 3.3V supply LVPECL output pair. LVPECL output pair. De s cription
3 4 6 7, 8, 14 9, 10 12, 13
CLK_SEL CLK0 CLK1 Vcc nQ1, Q1 nQ0, Q0
Input Input Input Power Output Output
Pulldown Pulldown Pulldown
Table 2. Pin Characteristics
S y mbo l Pa ra me te r C LK 0 , C LK 1 C LK _ EN C LK _ S EL Te s t Co nditio ns M in. Ty p. 3.2 pF 2.7 80 K o hm 80 M ax. Units
C IN
Inp ut C ap acitance
RP ULLUP RP ULLDO WN
Inp ut P ullup Resisto r Inp ut P ulld o wn Resisto r
3
PS8626A
05/01/03
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