|
|
Part: PI6C3Q991A-5J
Category:
Timing Circuits
-> Clock & Timing
Description: 750ps Accuracy, 3.3V, Balanced, 3.75 to 85 MHZ
Company: Pericom Semiconductor Corporation
Datasheet: Download PI6C3Q991A-5J datasheet File size : 292 kB
Request For quote: Find where to buy PI6C3Q991A-5J
Datasheet text preview:
3F0 FS VCCQ REF GND TEST 2F1
VCCN FB VCCN 2Q1 2Q0
3Q1 3Q0
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C3Q991A, PI6C3Q993A
3.3V Programmable Skew PLL Clock Driver SuperClock
Description
Features
· PI6C3Q99X family provides following products: PI6C3Q991A: 32-pin PLCC version PI6C3Q993A: 28-pin QSOP version · Inputs are 5V Tolerant · 4 pairs of programmable skew outputs · Low skew: 200ps same pair; 250ps all outputs · Selectable positive or negative edge synchronization: Excellent for DSP applications · Synchronous output enable · Input frequency: 3.75 MHz to 110 MHz · Output frequency: 15 MHz to 110 MHz · 2x, 4x, 1/2, and 1/4 outputs · 3 skew grades: PI6C3Q99x: tSKEW0 <750ps PI6C3Q99x-5: tSKEW0 <500ps PI6C3Q99x-2: tSKEW0 <250ps · 3-level inputs for skew and PLL range control · PLL bypass for DC testing · External feedback, internal loop filter · 12mA balanced drive outputs · Low Jitter: < 200ps peak-to-peak · Industrial temperature range · Pin-to-pin compatible with IDT QS5V991A and QS5V993A · Available in 32-pin PLCC and 28-pin QSOP
The PI6C3Q99X family, a high-fanout 3.3V PLL-based clock driver, is intended for high-performance computing and data-communication applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The PI6C3Q991A has 8 programmable skew outputs in 4 banks of 2, while the PI6C3Q993A has 6 programmable skew outputs and 2 zero skew outputs. Skew is controlled by 3-level input signals that may be hard-wired to appropriate HIGH-MID-LOW levels. When the GND/sOE pin is held LOW, all the outputs are synchronously enabled. However, if GND/sOE is held HIGH, all outputs except 3Q0 and 3Q1 are synchronously disabled. Furthermore, when the V CCQ /PE is held HIGH, all outputs are synchronized with the positive edge of the REF clock input. When VCCQ /PE is held LOW, all outputs are synchronized with the negative edge of REF. Both devices have LVTTL outputs with 12mA balanced drive outputs.
Pin Configurations PI6C3Q991A
REF VCCQ FS
PI6C3Q993A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
GND TEST 2F1 2F0 GND/sOE 1F1 1F0 VCCN 1Q0 1Q1 GND GND 2Q0 2Q1
3F1 4F0 4F1 VCCQ/PE VCCN 4Q1 4Q0 GND GND
4 5 6
32
1 32 31 30 29 28
7 27 8 26 32-Pin 9 25 J 10 24 11 23 12 22 13 21 14 15 16 17 18 19 20
2F0 GND/sOE 1F1 1F0 VCCN 1Q0 1Q1 GND GND
3F0 3F1 VCCQ/PE VCCN 4Q1 4Q0 GND 3Q1 3Q0 VCCN FB
28-Pin Q
1
PS8628A
02/06/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C3Q991A, PI6C3Q993A 3.3V Programmable Skew PLL Clock Driver SuperClock
Logic Block Diagrams
PI6C3Q991A
GND/sOE Skew Select 3 VCCQ/PE Skew Select REF FB 3 FS Skew Select 3 3 4F1:0 3 PLL Skew Select 3 3 3F1:0 4Q0 4Q1 3 2F1:0 3Q0 3Q1 3 1F1:0 2Q0 2Q1
REF FB 3 FS PLL Skew Select 3 3 3F1:0 4Q0 4Q1
PI6C3Q993A
GND/sOE
1Q0 1Q1
VCCQ/PE
Skew Select 3 3 1F1:0 Skew Select 3 3 2F1:0
1Q0 1Q1
2Q0 2Q1
3Q0 3Q1
Table 1. Pin Descriptions
Pin Name REF FB TEST(1) Type IN IN IN Reference Clock input Feedback Input When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew selections (see table 3) remain in effect. Set LOW for normal operation. Synchronous Output Enable. When HIGH, it stops clock outputs (except 3Q0 and 3Q1) in a LOW state 3Q0 or 3Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and GND/sOE is HIGH, the nF [1:0] pins act as output disable controls for individual banks when nF [1:0] = LL. Set GND/sOE LOW for normal operation. Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference clock. 3- level inputs for selecting 1of 9 skew taps or frequency range. Selects appropriate oscillator circuit based on anticipated frequency range. See table 2 4 output banks of 2 outputs, with programmable skew. On the PI6C3Q993A 4Q1:0 are fixed zero skew outputs. Functional De s cription
GND/sOE(1)
IN
VCCQ/ PE nF [1:0] FS nQ [1:0] VCCN VCCQ GND
IN IN IN OUT
PWR Power supply for output buffers PWR Power supply for phase locked loop and other internal circuitry PWR Ground
Note: 1. When TEST = MID and GND/sOE = HIGH, PLL remains active with nF[1:0] =LL functioning as an output disable control for individual output banks. Skew selections (see Table 3) remain in effect unless nF[1:0] = LL.
2
PS8628A 02/06/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C3Q991A, PI6C3Q993A 3.3V Programmable Skew PLL Clock Driver SuperClock
Programmable Skew
Output skew with respect to the REF input is adjustable to compensate for PCB trace delays, backplane propagation delays or to accommodate requirements for special timing relationships between clocked components. Skew is selectable as a multiple of a time unit tU which is of the order of a nanosecond (see Table 2). There are 9 skew configurations available for each output pair. These configurations are choosen by the nF1:0 control pins. In order to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW) are used, they are intended for but not restricted to hard-wiring. Undriven 3-level inputs default to the MID level. Where programmable skew is not a requirement, the control pins can be left open for the zero skew default setting. The Skew Selection Table (Table 3) shows how to select specific skew taps by using the nF1:0 control pins.
External Feedback
By providing external feedback, the PI6C3Q99x family gives users flexibility with regard to skew adjustment. The FB signal is compared with the input REF signal at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes.
Table 2. PLL Programmable Skew Range and Resolution Table
FS = LOW Timing unit calculatio n (t U ) VC O freq uency range (F N O M) S kew ad justment range(4 ) Max. ad justment Examp le 1, F N O M = 15 MHz Examp le 2 , F N O M = 2 5 MHz Examp le 3 , F N O M = 3 0 MHz Examp le 4 , F N O M = 4 0 MHz Examp le 5 , F N O M = 5 0 MHz Examp le 6 , F N O M = 8 0 MHz
(2 , 3 )
FS = M ID 1/(2 6 xF N O M ) 2 5 to 6 0 MHz ± 9 . 2 3 ns ± 83° ± 23% tU = 1. 5 4 ns tU = 1. 2 8 ns tU = 0 . 9 6 ns tU = 0 . 7 7 ns
FS = HIGH 1/(16 xF N O M ) 4 0 to 110 MHz ± 9 . 3 8 ns ± 135° ± 37%
Co mme nts
1/(4 4 xF N O M ) 15 to 3 5 MHz ± 9 . 0 9 ns ± 49° ± 14% tU = 1. 5 2 ns tU = 0 . 9 1ns tU = 0 . 7 6 ns
ns P hase d egrees % o f cycle time
tU = 1. 5 6 ns tU = 1. 2 5 ns tU = 0 . 7 8 ns
Notes: 2. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. Selecting the appropriate FS value based on input frequency range allows the PLL to operate in its `sweet spot' where jitter is lowest. 3. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q1:0, 2Q1:0, and the higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be the same as the VCO when the output connected to FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO frequency when the part is configured for a frequency multiplication by using a divided output as the FB input. 4. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example if a 4tU skewed output is used for feedback, all other outputs will be skewed 4tU in addition to whatever skew value is programmed for those outputs. `Max adjustment' range applies to output pairs 3 and 4 where ±6tU skew adjustment is possible and at the lowest FNOM value.
3
PS8628A
02/06/03
Others parts begin by pi
PI-1 PI-2 PI-3 PI-4 PI-5 PI-6 PI-7 PI-8 PI-9 PI-10 PI-11 PI-12 PI-13 PI-14 PI-15 PI-16 PI-17 PI-18 PI-19 PI-20 PI-21 PI-22 PI-23 PI-24 PI-25 PI-26 PI-27 PI-28 PI-29 PI-30 PI-31 PI-32 PI-33 PI-34 PI-35 PI-36 PI-37 PI-38 PI-39 PI-40 PI-41 PI-42 PI-43 PI-44 PI-45 PI-46 PI-47 PI-48 PI-49 PI-50 PI-51 PI-52 PI-53 PI-54 PI-55 PI-56 PI-57 PI-58 PI-59 PI-60 PI-61 PI-62 PI-63 PI-64 PI-65 PI-66
|
|
|
