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Part: PE4302-20MLP4x4-6000C
Category:
RF & Microwaves
-> Attenuators
-> Digital Step Attenuators (Monolithic)
Description: Product Description = 6 Bit, 50 Ohm 31.5 DB Range 0.5 Steps ;; Operating Frequency (MHz) = DC - 3000 ;; Insertionloss (dBm) = 2.0 ;; Input IP3 (dBm) = 45 ;; Attenuation Accuracy = +/-(0.3 + 4% of Atten. Setting) ;; Switchingspeed (uS) = 1 ;; Package Types = 20L MLPQ
Company: Peregrine Semiconductor Corp.
Datasheet: Download PE4302-20MLP4x4-6000C datasheet File size : 150 kB
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ADVANCED INFORMATION
PE4302
Product Description
The PE4302 is a high linearity, 6-bit RF Digital Step Attenuator "DSA" covering a 31.5 dB attenuation range in 0.5 dB steps. This 50-ohm RF DSA provides both parallel and serial CMOS control interface operates on a single 3volt supply and maintains high attenuation accuracy over frequency and temperature. It also has a unique control interface that allows the user to select an initial attenuation state at power-up. The PE4302 exhibits very low insertion loss and low power consumption. This functionality is delivered in a 4x4mm MLP footprint. The PE4302 is manufactured in Peregrine's patented Ultra Thin Silicon (UTSi) CMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 1. Functional Schematic Diagram
Parallel Control Serial Interface Power-Up Control RF Input
Unique RF Digital Attenuator 6-bit, 31.5 dB, DC 2.2 GHz
Features · Attenuation: 0.5 dB steps to 31.5 dB · Unique power-up state selection · High attenuation accuracy over temperature and frequency · Single-supply operation · Flexible parallel and serial programming interfaces · Positive CMOS control logic · 50 impedance · Very low power consumption · Packaged in a 4x4 MLP
Control Logic Interface
Switched Attenuator Array
RF Output
Table 1. Electrical Specifications @ +25 °C
Parameter
Operation Frequency Insertion Loss Attenuation Accuracy 1 dB Compression Input IP3 Return Loss Switching Speed IDD Total Supply Current 50% control to 0.5 dB of final value VDD = 3V
DC to 2.2 GHz
Test Conditions
Frequency
DC to 2.2 GHz
Minimum
DC 15 -
Typical
2.0 25 45
-
Maximum
2200 ±(0.2 + 3% of atten setting) ±(0.2 + 5% of atten setting) 1 300
Units
MHz dB dB dB dBm dBm dB µs µA
Any Bit or Bit Combination
DC to < 1.5 GHz 1.5 to 2.2 GHz 1 MHz to 2.2 GHz
Two-tone inputs up to +5 dBm
1 MHz to 2.2 GHz
DC to 2.2 GHz
-
PEREGRINE SEMICONDUCTOR CORP. |
http://www.peregrine-semi.com
Copyright Peregrine Semiconductor Corp. 2003
Page 1 of 9
PE4302
Advanced Information
Figure 2. Pin Configuration (Top View)
GND C0.5 C1 C2 C4
Table 3. Absolute Maximum Ratings
Symbol
V DD VI
Parameter/Conditions
Power supply voltage Voltage on any input Storage temperature range Operating temperature range Input power (50) ESD voltage (Human Body Model)
Min
-0.3 -0.3 -65 -40
Max
4.0 V DD + 0.3 150 85 33 200
Units
V V °C °C dBm V
20
19
18
17
C16 RF1 Data Clock LE
16
1 2 3 4 5 10
15
C8 RF2 P/S Vss/GND GND
TST TOP PI N VESD
20-lead MLPQ 4x4mm
Exposed Solder Pad (Bottom Side)
14 13 12 11
6
7
8
9
PUP1
PUP2
GND
VDD
VDD
Table 4. DC Electrical Specifications
Parameter
VDD Power Supply Voltage
Min
2.7
Typ
3.0
Max
3.3 300
Units
V µA V V
Table 2. Pin Descriptions
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
IDD Power Supply Current Digital Input High 0.7xVDD Digital Input Low
Pin Name
C16 RF1 Data Clock LE V DD PUP1 PUP2 V DD GND GND V s s /GND P/S RF2 C8 C4 C2 GND C1 C0.5
Description
Attenuation control bit, 16dB. RF port (Note 1). Serial interface data input. Serial interface clock input. Latch Enable input (Note 2). Power supply pin. Power-up selection bit, MSB. Power-up selection bit, LSB. Power supply pin. Ground connection. Ground connection. Negative supply voltage or GND connection(Note 3) Parallel/Serial mode select. RF port (Note 1). Attenuation control bit, 8dB. Attenuation control bit, 4dB. Attenuation control bit, 2dB. Ground connection. Attenuation control bit, 1dB. Attenuation control bit, 0.5dB.
0.3xVDD
Exposed Solder Pad Connection The exposed solder pad on the bottom of the package must be grounded for proper device operation. Electrostatic Discharge (ESD) Precautions When handling this UTSi device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 3. Latch-Up Avoidance Unlike conventional CMOS devices, UTSi CMOS devices are immune to latch-up. Switching Frequency The PE4302 has a maximum 25kHz switching rate when the internal -3V negative supply generator is used (pin 12=GND). The rate at which the PE4302 can be switched is not limited if an external -3V supply is provided. (Pin 12=VSS).
Note 1: Both RF ports must be DC blocked with an external series capacitor or held at 0VDC. 2: Latch Enable (LE) has an internal pullup resistor to VDD 3: Connect pin 12 to GND to enable -3V internal supply generator. Connect pin 12 to VSS (-3V) to bypass and disable internal -3V supply generator. See paragraph "Switching Frequency."
Copyright Peregrine Semiconductor Corp. 2003
File No. 70/0056~00D
| UTSi CMOS RFIC SOLUTIONS
Page 2 of 9
PE4302
Andvanced Information
Programming Options The PE4302 provides very flexible attenuation state programming options that include parallel and serial interfaces, and a unique programming interface for selection of the power-up attenuation state. Parallel/Serial Selection Either a parallel or serial interface can be used to control the PE4302. The "P/S" bit provides this selection, with P/S=LOW selecting the parallel interface and P/S=HIGH selecting the serial interface. Parallel Interface The parallel interface consists of six CMOScompatible control lines that select the desired attenuation state, as shown in Table 5. These inputs are buffered by a transparent latch that is controlled with the Latch Enable (LE) line. The latch appears transparent to parallel control line data when LE is held HIGH. When LE is taken LOW, data that meets the setup time is latched. The parallel interface timing requirements are defined by Figure 10 (Parallel Interface Timing Diagram) and Table 9 (AC Characteristics). Table 5. Truth Table Parallel Interface Mode
P/E 0 0 0 0 0 0 0 0 LE 1 1 1 1 1 1 1 1
into the shift register, a process that is independent of the state of the LE input. The LE input controls the latch. When LE is HIGH, the latch is transparent and the contents of the serial shift register control the attenuator. When LE is brought LOW, data in the shift register is latched. The shift register should be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data. The timing for this operation is defined by Figure 9 (Serial Interface Timing Diagram) and Table 8 (AC Characteristics). Power-up Control Settings The PE4302 always assumes a specifiable attenuation setting on power-up. This feature exists for both the Serial and Parallel modes of operation, and allows a known attenuation state to be established before an initial serial or parallel control word is provided. When the attenuator powers up in Serial mode (P/S=1), the six control bits are set to whatever data is present on the six parallel data inputs (C0.5 to C16). This allows any one of the 64 attenuation settings to be specified as the power-up state. When the attenuator powers up in Parallel mode (P/S=0) with LE=0, the control bits are automatically set to one of four possible values. These four values are selected by the two powerup control bits, PUP1 and PUP2, as shown in Table 6 (Power-Up Truth Table, Parallel Mode). Table 6. Power-Up Truth Table, Parallel Interface Mode
P/S
0 0 0 0 0
C16
0 0 0 0 0 0 1 1
C8
0 0 0 0 0 1 0 1
C4
0 0 0 0 1 0 0 1
C2
0 0 0 1 0 0 0 1
C1 C0.5
0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1
Attenuation State
Reference Loss 0.5 dB 1 dB 2 dB 4 dB 8 dB 16 dB 31.5 dB
LE
0 0 0 0 1
PUP2
0 1 0 1 X
PUP1
0 0 1 1 X
Attenuation State
Reference Loss 8 dB 16 dB 31 dB Defined by C0.5-C16
Note: Not all 64 possible combinations of C0.5-C16 are shown in table.
Serial Interface The serial interface is a 6-bit serial-in, parallel-out shift register buffered by a transparent latch. It is controlled by three CMOS-compatible signals: Data, Clock, and Latch Enable (LE). The Data and Clock inputs allow data to be serially entered
PEREGRINE SEMICONDUCTOR CORP. |
http://www.peregrine-semi.com
Note: Power up with LE=1 provides normal parallel operation with C0.5-C16, and PUP1 and PUP2 are not active.
Copyright Peregrine Semiconductor Corp. 2003
Page 3 of 9
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