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Part: EPF8013GM
Category:
Description: 10/100 Lan Module For DP83840A With Enhanced Common Attenuation
Company: PCA Electronics Inc.
Datasheet: Download EPF8013GM datasheet File size : 188 kB
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Datasheet text preview:
ELECTRONICS INC.
10/100 LAN Module For DP83840A with Enhanced Common Mode Attenuation EPF8013GM
· Optimized for DP83840A/DP83223 Chip Set · · Guaranteed to operate with 8 mA DC bias at 70°C · · Complies with or exceeds IEEE 802.3, 10 BT/100 BX Standards ·
Electrical Parameters @ 25° C
OCL @ 70°C 100 KHz, 0.1 Vrms 8 mA DC Bias Cable Side 3 5 0µ H Insertion Loss (dB Max.) 1-80 MHz 80-100 MHz 100-150 MHz 1-30 MHz Return Loss (dB Min.) 30-60 MHz 60-100 MHz Common Mode Rejection (dB Min.) 1-30 MHz 30-100 MHz 100-200 MHz Crosstalk (dB Min.) [Between Channels] 5-10 MHz 10-100 MHz
Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv Xmit -1 · -1 -1 -1 -3.5 -3 -18 -18 -12
Rcv Xmit -12 -10
Rcv Xmit Rcv Xmit Rcv Xmit Rcv -10 -40 -40 -35 -30 -30 -30 · -35 -35
Isolation : 1500 Vrms ·
Impedance : 100 · Rise Time : 3.0 nS Max. · * CMT : Optional
Receive Channel 1 7 5
Schematic
100 BX 15 16 10 BT 14 13
Transmit Channel 11 Isolation Transformer CMT* 12 10
2 1:1 3
6
Package
A J
PCA EPF8013GM Date Code Dim. Min. .970 .380 .223 .700 .003 .100 .500 .016 .008 .090 0° .025
Dimensions
(Inches) Max. Nom. .990 .400 .243 Typ. .020 Typ. .520 .022 .012 Typ. 8° .045 .030 .100 .092 .560 (Millimeters) Min. Max. Nom. 24.64 9.65 5.66 17.78 0.076 2.54 12.7 .406 .203 2.28 0° .635 25.15 10.16 6.17 Typ. .508 Typ. 13.20 .559 .305 Typ. 8° 1.14 .762 2.54 2.34 14.22
N
Pad Layout
Pin 1 I.D.
B
Q
P
D E
M
C
K L I
A B C D E F G H I J K L M N P Q
H
F
G
PCA ELECTRONICS, INC. 16799 SCHOENBORN ST. NORTH HILLS, CA 91343
CSF8013GMa Rev. Orig.
11/20/96
Product performance is limited to specified parameters. Data is subject to change without prior notice.
TEL: (818) 892-0761 FAX: (818) 894-5791 http://www.pca.com
ELECTRONICS INC.
10/100 LAN Module For DP83840A with Enhanced Common Mode Attenuation
The circuit below is a guideline for interconnecting PCA's EPF8013GM with National DP83840A and DP83223 twister chip set for 10/100 Mb/s applications. Further details can be obtained from the chip manufacturer application notes. This interface module offers the user two independent inputs : 1. The first pair (13/14) is for 10 Base-T transmit. 2. The second pair is for the 100 BX transmit. Typical insertion loss of the isolation transformer is 0.5dB. This parameter covers the entire spectrum of the encoded signals in 10/100 protocols. Under terminated conditions, to transmit a 2V pk-pk signal across the cable, you must adjust the TXREF resistor of the twister chip to get at least 2.12V pk-pk across pins 16-15. Note that significant low frequency response improvement can be obtained in the system (improving equalization effects) if the DC blocking capacitors were not used; this can only be done by choosing a different pinout for the 10 Base-T receiver side. This is accomplished without impacting any other behavior. If any user has a need to improve this feature, please consult with the PCA Technical support group. Parts similar to EPF8013GM are available from several LAN magnetics vendors. It is recommended that system designers do not use the receiver side center tap to ground, via a capacitor. This may worsen EMI, specifically if the secondary "common mode termination" is pulled to chassis ground as shown. The phantom resistors shown around the connector have been known to suppress unwanted radiation that unused wires pick up from the immediate environment. Their placement and use are to be considered carefully before a design is finalized. The "common mode termination" load of 75 shown from the center taps of the secondary may be taken to chassis ground via a cap of suitable value. This depends upon user's design, EMI margin etc. It is recommended that there be a neat separation of ground planes in the layout. It is generally accepted practice to limit the plane off at least 0.05 inches away from the chip side pins of EPF8013GM. There need not be any ground plane beyond this point. For best results, PCB designer should design the outgoing traces preferably to be 50 , balanced and well coupled to achieve minimum radiation from these traces.
Typical Application Circuit for UTP (Excerpts from NSC DP83840A application notes)
0.10µF {Note 1} +
1
1000pF 12.1 0.1µF {Note 1}
7
75 50
8 7 6 5 4
75
RXD
-
2
5 6
50
TXU
+ -
14 10 13 16 15
+ 12.1 12.1
12.1
RJ45*
12 11
2000V
3 2 1
1000pF
+
TXO PMRD
EPF8013GM
Isolation Cap
TD
-
RXI
DP83840A
+
DP83223
SD PMID
Chassis Ground
SD
+
Other pull down/up resistors not shown, for clarification please refer to National's application notes. Notes : 1. See text above for clarification. 2. *NIC Side is shown. Hub side connections will have crossover swapping pins 3-6 & 1-2.
RD
-
PCA ELECTRONICS, INC. 16799 SCHOENBORN ST. NORTH HILLS, CA 91343
CSF8013GMb
Rev. Orig.
11/20/96
TEL: (818) 892-0761 FAX: (818) 894-5791 http://www.pca.com
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