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Part: EPA1829AG
Category:
Description: 10 Base-t Interface Module With Enhanced Common Mode Attenuation
Company: PCA Electronics Inc.
Datasheet: Download EPA1829AG datasheet File size : 188 kB
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Datasheet text preview:
ELECTRONICS INC.
10 Base-T Interface Module with Enhanced Common Mode Attenuation EPA1829AG
· General Purpose 10 Base-T Filter Module · · Available in SMD, DIP and DILPackages · · Complies with or exceeds IEEE 802.3, 10 Base-T Requirements ·
Electrical Parameters @ 25° C
Cut-off Frequency (MHz) ± 1.0 MHz Xmit 17 Rcv 17 Insertion Loss (dB Max.) 1-10 MHz Xmit -1 Rcv -1 Return Loss (dB Min.) 5-10 MHz Xmit -15 Rcv -15 @ 20 MHz Xmit -7 Rcv -6 Attenuation (dB Min.) @ 25 MHz Xmit -19 Rcv -14 @ 30 MHz Xmit -30 Rcv -20 @ 40 MHz Xmit -35 Rcv -31 @ 50 MHz Xmit -40 Rcv -40 Common Mode Rejection (dB Min.) @ 100 MHz Xmit -30 Rcv -30 @ 200 MHz Xmit --Rcv --Crosstalk (dB Min.)
@ 1-10 MHz Xmit -30 Rcv -30
· Isolation : meets or exceeds 802.3 IEEE Requirements · Characteristic Filter Impedance : 100 · · *Referenced to the Output Level Fundamental Frequency @ 5 MHz · CMC is common to both channels ·
Schematic
Transmit Channel 1 2 3 1:1 LPF 14 15 8 1:1 10 16 6 LPF 7 9 Receive Channel 11
Package
A J
Pin 1 I.D. PCA EPA1829AG Date Code Dim. Min. .980 .260 .255 .700 .005 .100 .390 .017 .008 .090 0° .030
Dimensions
(Inches) Max. Nom. 1.00 .280 .275 Typ. .015 Typ. .410 .023 .012 Typ. 8° .050 .030 .100 .055 .440 .300 Typ. 7.62 Typ. (Millimeters) Min. Max. Nom. 24.89 6.60 6.48 17.78 .127 2.54 9.91 .432 .203 2.29 0° .762 25.4 7.11 6.99 Typ. .381 Typ. 10.41 .584 .305 Typ. 8° 1.27 .762 2.54 1.40 11.18
M
N
B
Q
Pad Layout
P
D C E K
R
L H F G
I
A B C D E F G H I J K L M N P Q R
PCA ELECTRONICS, INC. 16799 SCHOENBORN ST. NORTH HILLS, CA 91343
CSA1829AG
Rev. C
10/7/96
Product performance is limited to specified parameters. Data is subject to change without prior notice.
TEL: (818) 892-0761 FAX: (818) 894-5791 http://www.pca.com
ELECTRONICS INC.
10 Base-T Interface Module with Enhanced Common Mode Attenuation EPA1829AG
The circuit below is a guideline for interconnecting PCA's EPA1829AG with a typical 10 Base-T PHY chip over UTP cable. Further details of system design, such as chip pin-out, etc. can be obtained from the specific chip manufacturer. Typical insertion loss of the isolation transformer/filter is 0.7dB. This parameter covers the entire spectrum of the encoded signals in 10 Base-T protocols. However, the predistortion resistor network introduces some loss which has to be taken into account in determining how well your design meets the Standard Template requirements. Additionally, the following need to be considered while selecting resistor values : a. The filter needs 100 termination, thus the Thevenin's equivalent resistance seen by the filter looking into the transmit outputs from the chip must be equal to a value close to 100. The typical driver output impedance is 5. Thus choose R1 and R2 values that are lowered by 5 on each leg. Following these guidelines will guarantee that the return loss specifications are satisfied at all extremes of cable impedance (i.e. 85 to 115) while the module is installed in your system. b. That the template requirements are satisfied under the worst case Vcc (i.e. 4.5V), will impose a further constraint on resistor selection, in that they ought to be the minimum derived from the calculations. Add R3 for more flexibility in setting voltage levels at the outputs. Note that some systems have auto polarity detection and some do not. If not, be certain to follow the proper polarity. It is recommended that system designers ground the chip side center taps via a low voltage capacitor. Taking the cable side center taps to chassis via capacitors, is not recommended, as this will add cost without containing EMI. This may worsen EMI, specifically if the primary "common mode termination" is pulled to ground as shown. The pulldown resistors used around the RJ45 connector have been known to suppress unwanted radiation that unused wires pick up from the immediate environment. Their placement and use are to be considered carefully before a design is finalized. It is recommended that there be a neat separation of ground planes in the layout. It is generally accepted practice to limit the plane off at least 0.08 inches away from the chip side pins of EPA1829AG. There need not be any ground plane beyond this point. For best results, PCB designer should design the outgoing traces preferably to be 50, balanced and well coupled to achieve minimum radiation from these traces.
Typical Application Circuit for UTP with external Resistor Network
TX+ TXd+
R1 R2
16 1
R3
3 6 1 2
TX+ TX-
14 11
RJ45*
RX+ RX4 5 7 8
TX-
R1 R2
2 3
10 Base-T TXdPHY
RX+
EPA1829AG
6 8 7
9
RXChassis Ground
Notes : * Pin-outs shown are for multiport, DCE configurations : e.g. Hubs, Repeaters For NIC's, swap pins 3-6 with pins 1-2.
PCA ELECTRONICS, INC. 16799 SCHOENBORN ST. NORTH HILLS, CA 91343
100
CSA1829AG
Rev. C
10/7/96
TEL: (818) 892-0761 FAX: (818) 894-5791 http://www.pca.com
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