|
|
Part: M14020EJ5V0DS00
Category:
Memory
-> SRAM
-> SRAM
Description:
Company: NEC Electronics Inc.
Datasheet: Download M14020EJ5V0DS00 datasheet File size : 24 kB
Request For quote: Find where to buy M14020EJ5V0DS00
Datasheet text preview:
DATA SHEET
µPD4382162, 4382182, 4382322, 4382362
8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION SINGLE CYCLE DESELECT
Description
The µPD4382162 is a 524,288-word by 16-bit, the µPD4382182 is a 524,288-word by 18-bit, µPD4382322 is a 262,144word by 32-bit and the µPD4382362 is a 262,144-word by 36-bit synchronous static RAM fabricated with advanced CMOS technology using N-channel four-transistor memory cell. The µPD4382162, µPD4382182, µPD4382322 and µPD4382362 integrates unique synchronous peripheral circuitry, 2bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock input (CLK). The µPD4382162, µPD4382182, µPD4382322 and µPD4382362 are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory. ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State ("Sleep"). In the "Sleep" state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation. The µPD4382162, µPD4382182, µPD4382322 and µPD4382362 are packaged in 100-pin plastic LQFP with a 1.4 mm package thickness for high density and low capacitive loading.
MOS INTEGRATED CIRCUIT
Features
· 3.3 V (Chip) / 3.3 V or 2.5 V (I/O) Supply · Synchronous operation · Internally self-timed write control · Burst read / write : Interleaved burst and linear burst sequence · Fully registered inputs and outputs for pipelined operation · Single-Cycle deselect timing · All registers triggered off positive clock edge · 3.3 V or 2.5 V LVTTL Compatible : All inputs and outputs 5 · Fast clock access time : 3.8 ns (150 MHz), 4.0 ns (133 MHz) (µPD4382322, µPD4382362), 4.0 ns (133 MHz) (µPD4382162, µPD4382182) · Asynchronous output enable : /G · Burst sequence selectable : MODE · Sleep mode : ZZ (ZZ = Open or Low : Normal operation) · Separate byte write enable : /BW 1 - /BW4 (µPD4382322, µPD4382362), /BW1 - /BW2 (µPD4382162, µPD4382182), /BWE Global write enable : /GW · Three chip enables for easy depth expansion · Common I/O using three state outputs
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. M14020EJ5V0DS00 (5th edition) Date Published January 2000 NS CP(K) Printed in Japan
The mark 5 shows major revised points.
©
1999
µPD4382162, 4382182, 4382322, 4382362
5
Ordering Information
Part number Access Time ns Clock Frequency MHz 133 133 150 133 150 133 Core Supply Voltage V 3.3 ± 0.165 I/O Interface V 3.3 or 2.5 LVTTL 2 100-PIN PLASTIC LQFP (14 x 20) 1 Package Notes
µPD4382162GF-A75 µPD4382182GF-A75 µPD4382322GF-A67 µPD4382322GF-A75 µPD4382362GF-A67 µPD4382362GF-A75
4.0 4.0 3.8 4.0 3.8 4.0
Notes 1. Grade A75 is available in the µPD4382162GF and µPD4382182GF. 2. Grade A67 and A75 are available in the µPD4382322GF and µPD4382362GF.
2
Data Sheet M14020EJ5V0DS00
µPD4382162, 4382182, 4382322, 4382362
Pin Configurations (Marking Side)
/××× indicates active low signal. 100-PIN PLASTIC LQFP (14 x 20) [µPD4382162GF, µPD4382182GF]
/BWE /BW2 /BW1 /ADV /CE2 /GW CLK CE2 VDD
VSS
/AC
/CE
/AP
NC
NC
A6
A7
A8
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC NC NC VDDQ VSSQ NC NC I/O9 I/O10 VSSQ VDDQ I/O11 I/O12 NC VDD NC VSS I/O13 I/O14 VDDQ VSSQ I/O15 I/O16 I/OP2, NC NC VSSQ VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A18 NC NC VDDQ VSSQ NC I/OP1, NC I/O8 I/O7 VSSQ VDDQ I/O6 I/O5 VSS NC VDD ZZ I/O4 I/O3 VDDQ VSSQ I/O2 I/O1 NC NC VSSQ VDDQ NC NC NC
MODE
A5
A4
A3
A2
A1
A0
NC
NC
V DD
VSS
NC
A17
A10
A11
A12
A13
A14
A15
Remark Refer to Package Drawing for 1-pin index mark.
A16
A9
/G
Data Sheet M14020EJ5V0DS00
3
Others parts begin by m1
|
|
|
