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Part: M14019EJ5V0DS00
Category:
Memory
-> SRAM
-> SRAM
Description:
Company: NEC Electronics Inc.
Datasheet: Download M14019EJ5V0DS00 datasheet File size : 24 kB
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Datasheet text preview:
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4382161, 4382181, 4382321, 4382361
8M-BIT CMOS SYNCHRONOUS FAST SRAM FLOW THROUGH OPERATION
Description
The µPD4382161 is a 524,288-word by 16-bit, the µPD4382181 is a 524,288-word by 18-bit, the µPD4382321 is a 262,144-word by 32-bit and the µPD4382361 is a 262,144-word by 36-bit synchronous static RAM fabricated with advanced CMOS technology using N-channel four-transistor memory cell. The µPD4382161, µPD4382181, µPD4382321 and µPD4382361 integrate unique synchronous peripheral circuitry, 2-bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock input (CLK). The µPD4382161, µPD4382181, µPD4382321 and µPD4382361 are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory. ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State ("Sleep"). In the "Sleep" state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation. The µPD4382161, µPD4382181, µPD4382321 and µPD4382361 are packaged in 100-pin plastic LQFP with a 1.4 mm package thickness for high density and low capacitive loading.
Features
· Single 3.3 V power supply · Synchronous operation · Internally self-timed write control · Burst read / write : Interleaved burst and linear burst sequence · Fully registered inputs for flow through operation · All registers triggered off positive clock edge · LVTTL Compatible : All inputs and outputs · Fast clock access time : 8.5 ns (100 MHz), 9 ns (90 MHz) (µPD4382321, µPD4382361) 5 9 ns (90 MHz), 10 ns (83 MHz) (µPD4382161, µPD4382181) · Asynchronous output enable : /G · Burst sequence selectable : MODE · Sleep mode : ZZ (ZZ = Open or Low : Normal operation) · Separate byte write enable : /BW 1 - /BW4 (µPD4382321, µPD4382361), /BW1 - /BW2 (µPD4382161, µPD4382181), /BWE Global write enable : /GW · Three chip enables for easy depth expansion · Common I/O using three state outputs
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. M14019EJ5V0DS00 (5th edition) Date Published June 2000 NS CP(K) Printed in Japan
The mark 5 shows major revised points.
©
1999
µPD4382161, 4382181, 4382321, 4382361
Ordering Information
Part number Access Time ns Clock Frequency MHz 90 83 90 83 100 90 100 90 2 Core Supply Voltage V 3.3 ± 0.165 I/O Interface V 3.3 LVTTL 100-pin Plastic LQFP (14 x 20) 1 Package Notes
µPD4382161GF-A90
9.0 10.0 9.0 10.0 8.5 9.0 8.5 9.0
5
µPD4382161GF-A10 µPD4382181GF-A90
5
µPD4382181GF-A10 µPD4382321GF-A85 µPD4382321GF-A90 µPD4382361GF-A85 µPD4382361GF-A90
Notes 1. Grade A90 and A10 are available in the µPD4382161GF and µPD4382181GF 2. Grade A85 and A90 are available in the µPD4382321GF and µPD4382361GF
2
Data Sheet M14019EJ5V0DS00
µPD4382161, 4382181, 4382321, 4382361
Pin Configurations (Marking Side)
/××× indicates active low signal.
100-pin Plastic LQFP (14 x 20) [µPD4382161GF, µ µPD4382181GF]
/BWE /BW2 /BW1 /ADV /CE2 /GW CLK CE2 VDD VSS /CE /AC /AP NC NC A6 A7 A8 A9 /G
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC NC NC VDDQ VSSQ NC NC I/O9 I/O10 VSSQ VDDQ I/O11 I/O12 NC VDD NC VSS I/O13 I/O14 VDDQ VSSQ I/O15 I/O16 I/OP2, NC NC VSSQ VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A18 NC NC VDDQ VSSQ NC I/OP1, NC I/O8 I/O7 VSSQ VDDQ I/O6 I/O5 VSS NC VDD ZZ I/O4 I/O3 VDDQ VSSQ I/O2 I/O1 NC NC VSSQ VDDQ NC NC NC
V SS
VDD
A17
A10
A11
A12
A13
A14
A15
Remark Refer to Package Drawing for 1-pin index mark.
MODE
A16
NC
NC
NC
A5
A4
A3
A2
A1
A0
Data Sheet M14019EJ5V0DS00
3
Others parts begin by m1
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