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Part: EA-C10
Category:
ASICs
-> Gate Array
Description: 2.5- Volt, 0.25-micron (drawn) CMOS Embedded Array
Company: NEC Electronics Inc.
Datasheet: Download EA-C10 datasheet File size : 124 kB
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NEC Electronics Inc.
Preliminary
EA-C10 2.5-Volt, 0.25-Micron (drawn) CMOS Embedded Array
March 1997
Description
The high-speed 0.25 µm drawn (0.18 µm L-effective) EA-C10 embedded array family offers both support for embedded high-density macros as well as the short turnaround time of a gate array resulting in a time-tomarket advantage. In this product, NEC combines highperformance CMOS gate array primitives with diffused, embedded megafunctions such as RAM, ROM, CPU, DSP and analog cores. EA-C10 also uses a cell-based I/O structure that allows a flexible adaptation to the system requirements. State-ofthe-art interface macros for high-speed or special signaling systems are also supported, such as PCI, HSTL, GTL+, LVDS, p-ECL, and IEEE1394. Analog functions like DACs, ADCs and PLLs also can be incorporated within the I/O area.
Figure 1. Embedded Array Core Integration
Cell-Based I/O Cells
High Density Memory
High Density Cell-Based Compiled Memory
Core or Megafunction
Logic Function
Gate Array Primitives (Sea-of-Gate) Advanced Core and Analog Functions Gate Array Base Master
Analog Macro
Process
EA-C10 ASICs are manufactured with NEC's advanced titanium-silicide (Ti-Si) process. The chip layout may use between three and five metal layers (Al). As the EA-C10 ASIC family follows basically a gate array approach, it offers short turnaround times for silicon processing and lower development costs compared to cell-based ASICs. The turnaround time is kept short by fixing the embedded core locations and beginning prototype fabrication in parallel with place and route design steps. Table 1. EA-C10 Series Features and Benefits
EA-C10 Series Features · · · · · · · · · · · 0.25 µm drawn (0.18 µm L-effective) CMOS process Advanced embedded array architecture Available gate counts from 206K to 7 million gates Optimized 2.5V architecture (operates down to 1.8V) Significant low power dissipation of 0.14 µW/MHz/gate Ultra-high pin count using 40 µm pad pitch Special power rail structure, multi-oxide process Cell-based I/O structure including LVDS, HSTL, GTL+, PCI Embedding of analog macros including DACs, ADCs Advanced packages such as TapeBGA, Flip Chip+BGA NEC's OpenCAD® design environment
Applications
The EA-C10 family is ideal for applications where high density is mandatory and a short time-to-market path is required. For example, RAM-dominated designs can be realized with reduced die size and a reasonable turnaround time. EA-C10 is well-suited for designs that may require rework, because the logic function portion of the design uses gate array primitives created just by the final metal m a s k s . Typical applications include engineering workstations, telecommunications systems, advanced graphics and low power applications where very high performance is required.
EA-C10 Series Benefits Ultra-high density cell structure with high performance Fast TAT and high integration of embedded megafunctions Support for a wide range of high-complexity systems Highest speed at ultra-low power consumption New application possibilities and new system solutions Increased I/O density to achieve smaller die sizes Mixed 2.5V / true 3.3V I/O for full system compatibility Flexible adaptation to system requirements Mixed-signal design options Cost-effective and state-of-the-art packaging Flexible design flow for short design times
A12503EU1V0DS00
OpenCAD is a registered trademark of NEC Electronics Inc. All non-NEC trademarks are the property of their respective owners.
EA-C10
Table 2. Product Outline
Master (µPD69..) 3 layer Master (µPD69..) 4 layer Master (µPD69..) 5 layer* Gate count (available) Number of pads Utilization Toggle frequency (typ.) Internal Delay time Input Output Consumed power Internal Input Output Power supply voltage Operating temperature Interface level Technology
(40 µm pitch)
..101 ..121 ..141 206k 348
..102 ..122 ..142 338k 444
..103 ..123 ..143 497k 540
..104 ..124 ..144 690k 636
..105 ..125 ..145 1041k 780
..107 ..127 ..147 1611k 972
..109 ..129 ..149 2127k 1116
..111 ..131 ..151 2509k 1212
..112 ..132 ..152 3137k 1356
..113 ..133 ..153 3597k 1452
..114 ..134 ..154 4089k 1548
..115 ..135 ..155 6937k 2016
80% for 3-layer metal; 85% for 4-layer metal 1.1 GHz 59 ps (F/O = 1, L = 0 mm); 147.5 ps (F/O = 2, L = typ. average length) 79.9 ps (F/O = 2, L = 0 mm) (FI01) 1.363 ns (C L = 50 pF) (FO02) 0.14 µW/MHz/gate (2.5V); 0.07 µW/MHz/gate (1.8V) 1.66 µW/MHz (F/O = 2, L = 0 mm) 167 µW/MHz (C L = 15 pF) 2.5 V ± 0.2V (operation down to 1.8V possible) -40 to +85°C 2.5V / 3.3V CMOS level, LVTTL level, GTL+,HSTL, PCI, pECL Sea-of-gates 0.25 µm (drawn) silicon gate CMOS (0.18 L-effective), diffused embedded macros, 3, 4 or 5* metal layers
(F322 )
Note: *5th metal layer used for flip-chip packaging
Interface Macro Support
The EA-C10 interface area uses the cell-based (CB-C10) I/O structures that provide a variety of interface options, including both 2.5-volt and 3.3-volt full-swing interface buffers. For special applications, several high-speed I/O buffer types are available. These include 3.3-volt PCI cells, AGP for 66 MHz and 133 MHz applications, GTL (Gunning Transceiver Logic), HSTL (class 1,2,3,4) and pseudoECL (pECL) buffers. These high-speed buffers are available for special applications. Table 3 summarizes the available interface options. 2.5-Volt / 3.3-Volt Mixed I/O Interfacing. Although EA-C10 is a 2.5-volt optimized technology with thin gate oxide, NEC offers 3.3-volt-compatible I/O interfacing. The full-swing 3.3-volt interfacing is achieved through a multi-oxide process in the I/O area. The buffers for 2.5volt / 3.3-volt interface levels can be mixed. This is supported by the special power rail structure shown in Figure 2.
Figure 2. Power Rail Structure
I/O area for 2.5V only
VDDQ I/O area
increased internal cell area Internal Core
VDD (2.5V, 3.3V) VDDQ (ex. HSTL)
GND for internal power supply
2.5V I/O area
3.3V I/O area
mixed voltage I/O area
Drawing not to scale
HSTL / PCI Interfacing. A third power rail (VDDQ ) is available for interface types that require a reference voltage (such as HSTL, GTL+, and AGP). These buffers may also be located anywhere in the I/O area.
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EA-C10
Table 3. EA-C10 I/O Buffer Types
Buffer Type Standard I/O Interface Buffers Options and Possible Combinations Pull-up 50 k , 5 k / Pull-down 50 k Schmitt Trigger input Fail safe LVCMOS / LVTTL level Output buffers: Open drain Tri-state Low noise (slew-rate controlled) Driveability: 2.5V interface: 3, 6, 9, 12, 18, 24 mA/slot 3.3V interface: 3, 6, 9, 12, 24 mA/slot High-Speed I/O Buffers PCI (3.3V, up to 64 bit / 66 MHz) GTL / GTL+ pECL HSTL SSTL LVDS* AGP (66 MHz and 133 MHz) IEEE1394* USB*
Macro Library Support
The embedded array approach allows the combination of high-density cores with a prototype turnaround time equal to gate arrays. Megafunctions and memory blocks such as RAM and ROM can be embedded into the sea-of-gates area within the EA-C10 base master. The area used for the megafunctions is defined by pre-diffusion. The logical function is created by the final metalization masks. This enables the usage of a gate array master and the whole set of macros available in the cell-based technology CBC10. Cores from the BiCMOS family (QB-10) may also be embedded. Memory Macros. Various kinds of memory macros are available for EA-C10. Designers can select either gate array memory compilers using gate array cells or cellbased compilers which offer higher density and faster access times. Cell-based type memory blocks are generated based on advanced memory compiler tools and thus ensure highest flexibility for design requirements. The available memory types are described in Table 4. Table 4. CMOS-10 / EA-C10 Memory Compilers
Family Type High-speed Mode Async. Aysnc. High-speed Sync. Sync. Sync. EA-C10 High-density Sync. Sync. High-speed Sync. Sync. Super high-speed Sync. Ports 1 2 2 3 5 1 2 1 2 1 Maximum Size 8 Kbit 8 Kbit 16 Kbit 16 Kbit 8 Kbit 2K word x 32 bit 2K word x 64 bit 2K word x 64 bit 4K word x 64 bit 4K word x 64 bit CMOS-10/ EA-C10
Note: *Under development. Please check the availability of the advanced interfaces with your nearest NEC design center.
Block Library Support
EA-C10's functional blocks are designed to be backwardcompatible with previous families. Thus, an easy migration from previous designs is possible. The library is fully compatible with CMOS-10, the 0.25 µm (drawn) gate array familiy. The EA-C10 family offers a wide variety of advanced blocks, including combinational gates, shift registers, adders and counters. In addition, memory blocks such as RAM and ROM are provided. The EA-C10 primitive macros are available in up to four performance/power options per primitive. With a range of options available, popular design synthesis tools are able to make the optimal size/performance/power choice for each path.
All memory macros can be combined with a built-in-selftest (BIST) macro for easy and high-performance production testing.
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EA-C10
Analog Macros. A variety of A/D and D/A converters will be available for analog applications. Analog-to-digital converters (ADCs) are under development with a bit resolution of 7 to 12 bits and a frequency of 100 kHz (for general-purpose applications) up to 30 MHz. Digital-toanalog converters (DACs) will also be developed with resolutions of 7 to 12 bits and a frequency of 100 kHz to 220 MHz for high-speed conversion. Mega Macros. NEC offers a large set of megamacros and cores to cope with today's system requirements. Table 5 shows a subset of the macro portfolio.
Table 5. EA-C10 Mega Macro Library (subset listing)
Type CPU CPU CPU CPU Datapath DSP DSP DSP I/F peripheral I/F peripheral I/F peripheral I/F peripheral Description V30MZTM: 16-bit microprocessor V8xxTM: 32-bit RISC microcontroller (several derivates) ARM VR4xxxTM: 64-bit RISC microcontroller (several derivates) High-speed multiplier/accumulator OAK: digital signal processor PINE: digital signal processor SPRX: digital signal processor 16550: UART with FIFO and 16450 mode 4993: 8-bit parallel I/O real-time clock 71037: DMA Controller 71051: USART, 300k bit/s, full-duplex Type I/F peripheral I/F peripheral I/F peripheral I/F peripheral I/F peripheral I/F peripheral I/F peripheral I/F peripheral I/F peripheral I/F peripheral I/F peripheral I/F peripheral DPLL APLL Description 71054: programmable timer/counter 71055: programmable parallel interface (3x 8-bit) 71059: interrupt controller unit ATM (25 MHz, 155 MHz) CODEC (modem, voice) Ethernet 10/100 base IEEE 1284: bidirectional centronics IEEE1394: high speed serial bus MPEG2 PCI controller RAC: RAMBUS ASIC Cell USB: Universal Serial Bus interface Digital PLL (up to 250 MHz) Analog PLL (up to 500 MHz)
Packaging
The advanced pad pitch of 40 µm allows high-pin-count applications and gives a significant benefit for pad-limited designs. EA-C10, the new high-performance embedded array family, is supported by a variety of advanced packages. For lower pin counts (up to 376 pins), the standard QFP is available, including the heat-spreader package type to improve thermal characteristics.
Package Type Plastic BGA Tape BGA QFP Flip-Chip Chip Scale Maximum Pin/Ball Count 672 1088 376 (0.4 mm pitch) 2016 500
Plastic BGAs with up to 672 balls can help to cope with high-complexity system requirements by providing excellent electrical and thermal characteristics. Tape BGA packages support up to 1088 balls. NEC expands the package offering continuously with new advanced packages. For high-performance applications with high pin counts, the 2-layer tape BGA with enhanced electrical characteristics is available. Applications that require ultra-dense packages can be realized with the flipchip package. This technique can also be used for MultiChip Module (MCM) structures, where die mounting was previously necessary.
V30MZ, V8xx, and Vr4xxx are trademarks of NEC Corporation.
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EA-C10
CAD Support
NEC takes up the challenges of the new ultra-highdensity 0.25 µm technology by having close relationships with leading EDA vendors to fulfill the design requirements during the whole design flow. Fully supported by NEC's sophisticated OpenCAD design framework, EA-C10 maximizes design quality and flexibility while minimizing ASIC design time. NEC's OpenCAD system allows designers to combine the EDA industry's most popular third-party design tools with proprietary NEC tools, including those for advanced floorplanner, clock tree synthesis, automatic test pattern generation (ATPG), full-timing simulation, accelerated fault grading and advanced place and route algorithms. The latest OpenCAD system is open for sign-off using standard EDA tools. NEC offers RTL- and STA-(Static Timing Analysis) sign-off procedures to shorten the ASIC design cycle of high-complexity designs. Support of High-Speed Systems. High-speed systems require tight control of clock skew on the chip and between devices on a printed circuit board. CB-C10 provides two features to control clock skew: the Digital PLL (DPLL) working at frequencies up to 250 MHz for chip-to-chip skew minimization and Clock Tree Synthesis (CTS). CTS -- supported by an NEC proprietary design tool -- is used for clock skew management through the automatic insertion of a balanced buffer tree. The clock tree insertion method minimizes large-capacitive trunks and is especially useful with the hierarchical, synthesized design style being used for high-integration devices. RC values for actual net lengths of the clock tree are used for back annotation after place and route operations. A skew as low as ±60 ps can be achieved. Accurate Design Verification. Nonlinear timing calculation is a very important requirement of the highdensity, deep sub-micron ASIC designs. NEC makes use of the increased accuracy delivered by the nonlinear table look-up delay calculation methodology and offers consistent wire load models to ensure a high accuracy of the design verification. Design Rule Check. A comprehensive design rule check (DRC) program reports design rule violations as well as chip utilization statistics for the design netlist. The generated report contains such information as net counts, total pin and gate counts, and utilization figures. Layout. During design synthesis, wire load models are used to get delay estimations in a very early state of the design flow. In general, there's no need for customers to perform the floorplanning to meet the required timing. During layout, enhanced in-place optimization (IPO) features of the layout tools and engineering change order (ECO) capabilities of the synthesis tools are used to optimize critical timing paths defined by the given timing constraints. This feature can reduce the total design time.
Test Support
The EA-C10 family supports automatic test generation through a scan test methodology. It includes internal scan, boundary scan (JTAG) and built-in-self-test (BIST) architecture for easy and high-performance production RAM testing. This allows higher fault coverage, easier testing and faster development time. Test of embedded megamacros is supported from NEC's test bus concept, which allows the use of predefined test pattern sets for integrated core macros.
Supplemental Publications
This data sheet contains preliminary specifications and operational data for the EA-C10 embedded array family. Additional information is available in NEC's EA-C10 Design Manual, Block Library and other related documents. Please refer also to the CMOS-10 and CB-C10 data sheets to get more information about 0.25 µm gate array and cell-based ASIC products. Please contact your local NEC design center for additional information; see the back of this data sheet for locations and telephone numbers.
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