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Part: E949PCASM
Category:
Others
Description: Clc949 Evaluation Board
Company: National Semiconductor Corporation
Datasheet: Download E949PCASM datasheet File size : 292 kB
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escription The Comlinear E949PCASM Evaluation board is designed to support simple and effective evaluation of the CLC949 Analog-to-Digital Converter. To operate the converter you need only supply power, a clock and a signal to be digitized. The evaluation board uses a common Eurocard connector to make the power, ground and data connections with the rest of the evaluation system. Options exist on the board to use an amplifier based input to the converter, a transformer coupled input, or direct input, as well as options to generate a clock from a sinusoidal source or to use a suitable CMOS clock. The bias points for the converter can be selected via a DIP switch. For a complete description of these various options, please refer to the CLC949 datasheet. Default Configuration The CLC949 Evaluation board is shipped configured for options 2 and 4 (DC coupled input using amplifiers, CMOS clock generator enabled). The output data format is offset binary and the bias point is selected to be 200µA, allowing 20MHz operation. Clock Generation The evaluation circuitry includes a clock generation circuit that will convert a sinusoidal input to a CMOS clock for use by the CLC949. When using this option, the clock signal that is provided should be 2-3Vpp (1014dBm). For best results when digitizing high speed input signals, the converter must have a very low jitter clock. To generate this the sinusoidal input must have very low phase noise. In a laboratory environment, Comlinear suggests the use of a low phase noise synthesizer such as the HP8662 or the HP8643 as a clock source. There is also an option that will enable you to provide a TTL or CMOS clock directly to the board. The clock is provided through an SMA connector, regardless of the clocking option chosen. To enable the input of a digital clock, remove the three jumpers labeled OPT4 and insert a jumper at the point labeled OPT1-3. These jumpers can be found on the opposite side of the board to the CLC949 and a surface mount 0 resistors.
CLC949 Evaluation Board
Part Number E949PCASM
August 1996
Analog Input Conditioning The CLC949 requires a differential input signal, centered around a bias point of approximately 2.25V The evaluation board offers three options for providing this input:
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Option 1 uses a transformer to phase split the input signal and to provide the appropriate offset voltage. This option will result in the lowest distortion signal for input frequencies of 1MHz or higher. Since the transformer is not able to pass frequencies lower than about 50kHz, this option is not a good choice if your signal must be DC coupled. If you want to use this option, install the transformer and the two jumpers labeled OPT1, and remove the three jumpers labeled OPT2. All of these jumpers can be found on the back side of the board. The transformer shipped with the board is a 1:1 transformer, therefore the input to it should be 2Vpp in order to obtain a full scale output. Option 2 uses an amplifier based circuit to perform the phase splitting and DC offset. This circuit is described in more detail in the CLC949 datasheet. Option 2 is the default condition in which the board is shipped. Using this option, a 2Vpp signal, with no DC offset is applied to the input SMA to obtain a full scale output. Option 3 requires that you provide a differential input signal with the proper offsets to the SMA connectors labeled +VIN and -VIN. To enable this option, remove the three jumpers labeled OPT2 and install the jumpers labeled OPT3.
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DATA and Clock Outputs The CLC949 Evaluation board is equipped with 74F574 latched which latch the CLC949 output data and drive the Eurocard connector. An inverted version of the A/D clock is also provided on the Eurocard connector. The output data format of the CLC949 is selectable between Offset Binary or Twos Complement via the Jumper OPT6. For Offset binary operation install the jumper in the location OPT6A, two's complement is achieved by use of OPT6B. These jumpers can be found on the front of the board, just above the CLC949 chip.
© 1996 National Semiconductor Corporation
Printed in the U.S.A.
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Bias Control The CLC949 offers you the ability to make a tradeoff between dynamic performance and power dissipation. This can be done by selecting one of three discrete bias points with the DIP switch on the board, or by selecting Option 5 which allows analog control of the bias current through the selection of R23. The bias point can be selected according to the following table: SW1A ON OFF ON OFF SW1B ON OFF OFF ON Bias Point Low Bias Medium Bias High Bias Set with R23
If you select Option 5, you must install the jumper labeled OPT5. Please refer to the CLC949 datasheet for assistance in selecting an appropriate value for R23.
Top (Silk)
Bottom (Silk)
Top (Metal)
Bottom (Metal)
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Layer 2 (Negative)
Layer 3 (Negative)
PIN DESCRIPTIONS
PIN# A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 Function NC GND NC NC NC NC 2V BIAS 2V BIAS 2V BIAS 2V BIAS 2V BIAS 2V BIAS 2V BIAS 2V BIAS 2V BIAS 2V BIAS PIN# B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 Function NC GND NC BC1 (IN) BC0 (IN) NC D1 (MSB) D2 D3 D4 D5 D6 D7 D8 D9 D10) PIN# A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 Function 2V BIAS 2V BIAS GND 2V BIAS NC NC NC NC NC NC GND GND -5V (IN) -5V (IN) +5V (IN) +5V (IN) PIN# B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 Function D11 D12 (LSB) GND DR NC NC NC NC NC NC GND GND -5V (IN) -5V (IN) +5V (IN +5V (IN
3
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CLC949 Evaluation Board (P/N 730058 Rev. A)
Z1
NC
VDDA
VDDA
VDDD
VDDD
VREFPO
VREFNO
VDDA
VDDD
CLK
BC1
GNDA GNDA
GNDA
GNDA
GNDD
GNDD
GNDD
MSBINV
OE\
D1(MSB)
D2
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CLC949 Eval Board
Z2
C16 2.2U C15 2.2U
C1 2.2U
Z3
CON64
Data Ready
J1
32B 31B 30B 29B 28B 27B 26B 25B 24B 23B 22B 21B 20B 19B 18B 17B 16B 15B 14B 13B 12B 11B 10B 9B 8B 7B 6B 5B 4B 3B 2B 1B 100 B 50 B DR F
+5V
32A 31A
-5V
30A R32 29A 3K
G ND
28A 27A 26A 25A 24A 23A 22A 21A 20A R33 2K
VREFMO VREFP BCO D12(LSB) D11 D10 D9 D8 D7 D6 D5 D4 D3 VREFN VREFPC VREFNC NC BIASC GNDA VINP VINN GNDA
C17 .1U
G ND
LSB F D1 F D3 F D4 F D5 F D6 F D7 F D8 F D9 F D10 F D11 F MSB F
4
19A 18A 17A 16A 15A 14A 13A 12A 11A 10A 9A 8A 7A 6A 5A 4A 3A
G ND
2A 1A
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